MV8870/MV8870-1

DS3140-2.1

MV8870 / MV8870-1

INTEGRATED DTMF RECEIVER

DIGITAL

DETECTION

ALGORITHM

CODE

CONVERTER

AND LATCH

HIGH GROUP FILTER

DIAL TONE FILTER

LOW GROUP FILTER

ZERO

CROSSING

DETECTORS

STEERING LOGIC

CHIP

CLOCKS

BIAS CIRCUIT

CHIP

POWER

CHIP

BIAS

1(1)

2(2)

3(3)

IN+

IN-

18(28)

9(14)

REF

4(5)

FLT

(22)

OSC1

7(12)

OSC2

8(13)

(21)

ESt

16(26)

StD

15(25)

St/GT

17(27)

TOE

10(16)

14(20)

13(19)

12(18)

11(17)

(9)

FHT

(8)

6(10)

SEL

5(7)

Figure 2: Functional block diagram (Pin numbers in brackets refer to HP package)

Figure 1: Pin connections - top view

REF

SEL

FHT

StD

FLT

IN-

IN+

St/GT

ESt

OSC1

OSC2

HP28

IN+

IN-

REF

SEL

OSC1

OSC2

St/GT

ESt

StD

TOE

DG18

DP18

MP18

The MV8870 / MV8870-1 is a complete DTMF receiver

integrating both the bandsplit filter and digital decoder
functions, fabricated in GPS's double-poly ISO2-CMOS
technology. The filter section uses switched capacitor
techniques for high and low group filters; the decoder uses
digital counting techniques to detect and decode all 16 DTMF
tone pairs into a 4-bit code.

External component count is minimised by on-chip

provision of a differential input amplifier, clock oscillator and
latched 3-state bus interface.

The MV8870 and MV8870-1 are functionally identical, but

differ in Electrical Characteristics.

FEATURES

Complete DTMF Receiver

Low Power Consumption

Internal Gain Setting Amplifier

Adjustable Guard Time

Central Office Quality

APPLICATIONS

Receiver Systems for BT or CEPT Specifications

Paging Sytems

Repeater Systems / Mobile Radio

Credit Card Systems

Remote Control

ADVANCE INFORMATION

MV8870/MV8870-1

FUNCTIONAL DESCRIPTION

The MV8870 / MV8870-1 monolithic DTMF receiver offers

small size, low power consumption and high performance. Its
architecture consists of a bandsplit filter section, which
separates the high and low tone groups, followed by a digital
counting section which verifies the frequency and duration of
the received tones before passing the corresponding code to
the output bus.

FILTER SECTION

Separation of the low-group and high-group tones is

achieved by applying the DTMF signal to the inputs of two
sixth-order switched capacitor band-pass filters, the
bandwidths of which correspond to the low and high group
frequencies. The filter section also incorporates notches at 350
and 440 Hz for exceptional dial tone rejection (see Fig.3). Each
filter is followed by a single order switched capacitor filter
section which smooths the signals prior to limiting. Limiting is
performed by high-gain comparators which are provided with
hysteresis to prevent detection of unwanted low-level signals.
The outputs of the comparators provide full rail logic swings at
the trequencies of the incoming DTMF signals.

For testing and monitoring, the high and low group filter

and zero crossing detector outputs are made available via
FHT, FH, FLT and FL (HP package only).

DECODER SECTION

Following the filter section is a decoder employing digital

counting techniques to determine the frequencies ot the
incoming tones and to verify that they correspond to standard
DTMF frequencies. A complex averaging algorithm protects
against tone simulation by extraneous signals such as voice
while providing tolerance to small frequency deviations and
variations. This averaging algorithm has been developed to
ensure an optimum combination of immunity to talk-off and
tolerance to the presence of interfering frequencies (third
tones) and noise. When the detector recognises the
simultaneous presence of two valid tones (this is referred to as
the `Signal Condition' in some industry specifications) the Early
Steering output (ESt) will go to an active state. Any
subsequent loss of signal condition will cause the ESt pin to go
to its inactive state (see Fig.5).

STEERING CIRCUIT

Before registration of a decoded tone-pair, the receiver

checks for a valid signal duration (referred to as (character
recognition condition). This check is performed by an external
RC time constant driven by ESt. A logic high on ESt causes the
voltage at the SVGT pin (V

St/GT

) to rise as the capacitor

discharges (see Figs.4 and 5).

Provided signal condition is maintained (ESt remains high)

for the validation period (t

GTP

), VSUGT reaches the threshold

(VTSt) of the steering logic which allows it to register the tone
pair and strobe the corresponding 4-bit code into the output
latch (see Fig.6). At this point the SVGT pin is activated as an
output and drives V

St/GT

to V

(see Fig.5).

St/GT continues to drive high as long as ESt remains high.

After a short delay (t

) to allow the output latch to settle, the

delayed steering output pin (StD) goes high to indicate that the
code for a new received tone-pair is available. The contents of
the output latch are output onto the output bus (Q1 to Q4 pins)
when the three-state output enable (TOE) pin is high.

The steering circuit works in reverse to validate the

interdigit pause between signals. Thus as well as rejecting
signals too short to be considered valid, the receiver will
tolerate signal interruptions (drop-out) too short to be
considered a valid pause. This facility, together with the
capability of selecting the steering time constants externally,
allows the designer to tailor performance to meet a wide
variety of system requirements.

St/GT

ESt

StD

MV8870/
MV8870-1

GTA

= RC In {V

�

TSI

}

GTP

= RC In {V

�

- V

TSU

)}

Figure 4: Basic Steering Circuit

B C

ATTENUATION

(dB)

FREQUENCY (Hz)

200

400

600

800

1000

1200

1400

1600

1800

2000

Precise

Dial Tones

X = 350 Hz

Y = 440 Hz

DTMF Tones

A = 697 Hz

B = 770 Hz

C = 852 Hz

D = 941 Hz

E = 1209 Hz

F = 1336 Hz

G = 1477 Hz

H = 1633 Hz

Figure 3: Filter response

MV8870/MV8870-1

APPLICATIONS

A simple application circuit is shown in Fig.7. This has a

symmetric guard time circuit, a single-ended analog input and
a dedicated crystal oscillator.

GUARD TIME ADJUSTMENT

In many situations not requiring seperate selection of tone

duration and interdigit pause, the simple steering circuit shown
in Fig.7 is applicable. Component values are chosen according
to the formulae (see Figs. 4, 8a and 8b):-

REC

= t

+ t

GTP

= t

+ t

GTA

The value of t

is a device parameter (see Dynamic

Characteristics and Fig.5) and t

REC

is the minimum signal

duration to be recognised by the receiver. Likewise t

is a

device parameter (Fig.5) and t

is the minimum time taken to

recognise an interdigit pause. A value for C2 of 0.1

�

-F is

recommended for most applications, leaving R3 to be selected
by the designer.

Different steering arrangements may be used to select

independantly the guard times for tone present (t

GTP

) and tone

absent (t

GTA

). This may be necessary to meet system

specifications which place both accept and reject limits on both
tone duration and interdigit pause. Guard Time adjustment
also allows the designer to tailor system parameters such as
talk-off and noise immunity. Increasing t

REC

improves talk-off

performance since it reduces the probability that tones
simulated by speech will maintain signal conditions long
enough to be registered. Alternatively a relatively short t

REC

wim a long t

would be appropriate for extremely noisy

environments where fast acquisition time and immunity to tone
drop-outs are required. Design information for guard time
adjustment is shown in Figs. 8a and 8b.

TONE N

TONE N + 1

TSt

t < t

GTP

t < t

GTP

t = t

GTP

t = t

GTA

t = t

GTA

t = t

GTP

t < t

GTA

PStD

TONE N

TONE N + 1

DECODED TONE N-1

TONE N

TONE N + 1

ESt

St/GT

StD

CODE

CONVERTER

LATCH

OUTPUTS

TOE

Q1 - Q4

EXPLANATION OF EVENTS
A, Tone bursts detected, but tone duration invalid and output latch unchanged.
B. Tone N detected, tone duration valid, output latch updated and new data signalled by
StD.
C. End of tone N detected, tone absent duration valid, but output latch updated until next
valid tone.
D. Outputs switched to high impedance.
E. Tone N + 1 detected, tone duration valid, tone decoded, output latch updated
(although outputs are currently high impedance) and new data signalled by StD.
F. Acceptable dropout of tone N + 1, tone absent duration invalid, StD and output latch
unchanged.
G. End of tone N + 1 detected, tone absent duration valid, StD goes low but output latch
not updated until next valid tone.

NOTES
1. t

time for valid tone present is

a device parameter (see Electrical
Characteristics).
2. t

time for valid tone absent is

a device parameter (see Electrical
Characteristics).
3. t

GTP

and t

GTA

are adjustable via

external RC network at pins 16
and 17 (see Fig. 4).
4. t

PSID

and t

are propogation

delays given in Electrical
Characteristics.

Figure 5: Timing diagram

MV8870/MV8870-1

LOW

HIGH

DIGIT

TOE

SELECT = L

SELECT = H

697

1209

697

1336

697

1477

770

1209

770

1336

770

1477

852

1209

852

1336

852

1477

941

1209

941

1336

941

1477

697

1633

770

1633

852

1633

941

1633

Any

Figure 6: Functional decode table

Figure 8a: Guard time adjustment (t

GTP

< t

GTA

)

Figure 8b: Guard time adjustment (t

GTP

> t

GTA

)

IN+

IN-

REF

SEL

OSC1

OSC2

St/GT

ESt

StD

TOE

DTMF
OUTPUT

R1, R2 = 100k

�

R3 = 300k

�

C1, C2 = 0.1

�

X = 3.579545MHz

�

0.1%

DECODED
OUTPUT

}

MV8870/
MV8870-1

Figure 7: Simple application circuit; single ended input

St/GT

ESt

StD

MV8870/
MV8870-1

GTA

= R1C In {V

�

TSt

}

GTP

= R

C In {V

�

- V

TSt

]}

= R1R2

�

{R1 + R2}

St/GT

ESt

StD

MV8870/
MV8870-1

GTA

= R

C In {V

�

TSt

}

GTP

= R1C In {V

�

- V

TSt

]}

= R1R2

�

{R1 + R2}

Электронный компонент: MV8870