Document Outline

• Features
  • Figure 1 - MVTX2602 System Block Diagram
• Description
• 1.0 Block Functionality
  • 1.1 Frame Data Buffer (FDB) Interfaces
  • 1.2 10/100 MAC Module (RMAC)
  • 1.3 CPU Interface Module
  • 1.4 Management Module
  • 1.5 Frame Engine
  • 1.6 Search Engine
  • 1.7 LED Interface
  • 1.8 Internal Memory
• 2.0 System Configuration
  • 2.1 Management and Configuration
  • 2.2 Managed Mode
    • Figure 2 - Overview of the MVTX2602 CPU Interface
  • 2.3 Register Configuration, Frame Transmission, and Frame Reception
    • 2.3.1 Register Configuration
    • 2.3.2 Rx/Tx of Standard Ethernet Frames
    • 2.3.3 Control Frames
  • 2.4 Unmanaged Mode
  • 2.5 I�C Interface
    • Figure 3 - Data Transfer Format for I�C Interface
    • 2.5.1 Start Condition
    • 2.5.2 Address
    • 2.5.3 Data Direction
    • 2.5.4 Acknowledgment
    • 2.5.5 Data
    • 2.5.6 Stop Condition
  • 2.6 Synchronous Serial Interface
    • 2.6.1 Write Command
    • 2.6.2 Read Command
• 3.0 MVTX2602 Data Forwarding Protocol
  • 3.1 Unicast Data Frame Forwarding
  • 3.2 Multicast Data Frame Forwarding
  • 3.3 Frame Forwarding To and From CPU
• 4.0 Memory Interface
  • 4.1 Overview
    • Figure 4 - MVTX2602 SRAM Interface Block Diagram (DMAs for 10/100 Ports Only)
  • 4.2 Detailed Memory Information
  • 4.3 Memory Requirements
• 5.0 Search Engine
  • 5.1 Search Engine Overview
  • 5.2 Basic Flow
  • 5.3 Search, Learning, and Aging
    • 5.3.1 MAC Search
    • 5.3.2 Learning
    • 5.3.3 Aging
    • 5.3.4 VLAN Table
      • Table 1 - VLAN Index Mapping Table
      • Table 2 - VLAN Index Port Association Table
  • 5.4 MAC Address Filtering
  • 5.5 Quality of Service
  • 5.6 Priority Classification Rule
    • Figure 5 - Priority Classification Rule
  • 5.7 Port and Tag Based VLAN
    • 5.7.1 Port-Based VLAN
      • Table 3 - PVMAP Register
    • 5.7.2 Tag-Based VLAN
  • 5.8 Memory Configurations
    • Table 4 - Supported Memory Configurations (SBRAM Mode)
    • Figure 6 - Options for Memory Configuration
    • Figure 7 - Memory Configuration for 1 Bank, 1 Layer, 1MB Total
    • Figure 8 - Memory Configuration for: 1 Bank, 2 Layers, 2MB Total
    • Figure 9 - Memory Configuration for 1 Bank, 1 Layer, 2MB
• 6.0 Frame Engine
  • 6.1 Data Forwarding Summary
  • 6.2 Frame Engine Details
    • 6.2.1 FCB Manager
    • 6.2.2 Rx Interface
    • 6.2.3 RxDMA
    • 6.2.4 TxQ Manager
  • 6.3 Port Control
  • 6.4 TxDMA
• 7.0 Quality of Service and Flow Control
  • 7.1 Model
    • Table 5 - Two-dimensional World Traffic
  • 7.2 Four QoS Configurations
    • Table 6 - Four QoS Configurations for a 10/100Mbps Port
  • 7.3 Delay Bound
  • 7.4 Strict Priority and Best Effort
  • 7.5 Weighted Fair Queuing
  • 7.6 Rate Control
  • 7.7 WRED Drop Threshold Management Support
    • Table 7 - WRED Drop Thresholds
  • 7.8 Buffer Management
    • Figure 10 - Buffer Partition Scheme Used to Implement MVTX2602 Buffer Management
    • 7.8.1 Dropping When Buffers Are Scarce
    • 7.8.2 MVTX2602 Flow Control Basics
    • 7.8.3 Unicast Flow Control
    • 7.8.4 Multicast Flow Control
  • 7.9 Mapping to IETF Diffserv Classes
    • Table 8 - Mapping between MVTX2602 and IETF Diffserv Classes for 10/100 Ports
    • Table 9 - MVTX2602 Features Enabling IETF Diffserv Standards
• 8.0 Port Trunking
  • 8.1 Features and Restrictions
  • 8.2 Unicast Packet Forwarding
  • 8.3 Multicast Packet Forwarding
  • 8.4 Unmanaged Trunking
• 9.0 Port Mirroring
  • 9.1 Port Mirroring Features
  • 9.2 Setting Registers for Port Mirroring
• 10.0 GPSI (7WS) Interface
  • 10.1 GPSI connection
    • Figure 11 - GPSI (7WS) Mode Connection Diagram
  • 10.2 SCAN LINK and SCAN COL interface
    • Figure 12 - SCAN LINK and SCAN COLLISON Status Diagram
• 11.0 LED Interface
  • 11.1 LED Interface Introduction
  • 11.2 Port Status
  • 11.3 LED Interface Timing Diagram
    • Figure 13 - Timing Diagram of LED Interface
• 12.0 Hardware Statistics Counter
  • 12.1 Hardware Statistics Counters List
  • 12.2 IEEE 802.3 HUB Management (RFC 1516)
    • 12.2.1 Event Counters
      • 12.2.1.1 Readable octet
      • 12.2.1.2 Readable Frame
      • 12.2.1.3 FCS Errors
      • 12.2.1.4 Alignment Errors
      • 12.2.1.5 Frame Too Longs
      • 12.2.1.6 Short Events
      • 12.2.1.7 Runts
      • 12.2.1.8 Collisions
      • 12.2.1.9 Late Events
      • 12.2.1.10 Very Long Events
      • 12.2.1.11 Data Rate Misatches
      • 12.2.1.12 AutoPartitions
      • 12.2.1.13 TotalErrors
  • 12.3 IEEE � 802.1 Bridge Management (RFC 1286)
    • 12.3.1 Event Counters
      • 12.3.1.1 InFrames
      • 12.3.1.2 OutFrames
      • 12.3.1.3 InDiscards
      • 12.3.1.4 DelayExceededDiscards
      • 12.3.1.5 MtuExceededDiscards
  • 12.4 RMON � Ethernet Statistic Group (RFC 1757)
    • 12.4.1 Event Counters
      • 12.4.1.1 Drop Events
      • 12.4.1.2 Octets
      • 12.4.1.3 BroadcastPkts
      • 12.4.1.4 MulticastPkts
      • 12.4.1.5 CRCAlignErrors
      • 12.4.1.6 UndersizePkts
      • 12.4.1.7 OversizePkts
      • 12.4.1.8 Fragments
      • 12.4.1.9 Jabbers
      • 12.4.1.10 Collisions
      • 12.4.1.11 Packet Count for Different Size Groups
  • 12.5 Miscellaneous Counters
• 13.0 Register Definition
  • 13.1 MVTX2602 Register Description
  • 13.2 Directly Accessed Registers
    • 13.2.1 INDEX_REG0
    • 13.2.2 INDEX_REG1 (only needed for 8-bit mode)
    • 13.2.3 DATA_FRAME_REG
    • 13.2.4 CONTROL_FRAME_REG
    • 13.2.5 COMMAND&STATUS Register
    • 13.2.6 Interrupt Register
    • 13.2.7 Control Command Frame Buffer1 Access Register
    • 13.2.8 Control Command Frame Buffer2 Access Register
  • 13.3 Indirectly Accessed registers
    • 13.3.1 Group 0 Address) MAC Ports Group
      • 13.3.1.1 ECR1Pn: Port N Control Register
      • 13.3.1.2 ECR2Pn: Port N Control Register
    • 13.3.2 (Group 1 Address) VLAN Group
      • 13.3.2.1 AVTCL � VLAN Type Code Register Low
      • 13.3.2.2 AVTCH � VLAN Type Code Register High
      • 13.3.2.3 PVMAP00_0 � Port 00 Configuration Register 0
      • 13.3.2.4 PVMAP00_1 � Port 00 Configuration Register 1
      • 13.3.2.5 PVMAP00_2 � Port 00 Configuration Register 2
    • 13.3.3 PVMAP00_3 � Port 00 Configuration Register 3
    • 13.3.4 Port Configuration Registers
      • 13.3.4.1 PVMODE
      • 13.3.4.2 PVROUTE 0
      • 13.3.4.3 PVROUTE1
      • 13.3.4.4 PVROUTE2
      • 13.3.4.5 PVROUTE3
      • 13.3.4.6 PVROUTE4
      • 13.3.4.7 PVROUTE5
      • 13.3.4.8 PVROUTE6
      • 13.3.4.9 PVROUTE7
    • 13.3.5 Group 2 Address Port Trunking Groups
      • 13.3.5.1 TRUNK0_L � Trunk group 0 Low (Managed mode only)
      • 13.3.5.2 TRUNK0_M � Trunk group 0 Medium (Managed mode only)
    • 13.3.6 TRUNK0_H � Trunk group 0 High (Managed mode only)
    • 13.3.7 TRUNK0_MODE� Trunk group 0 mode
    • 13.3.8 TRUNK0_HASH0 � Trunk group 0 hash result 0 destination port number
    • 13.3.9 TRUNK0_HASH1 � Trunk group 0 hash result 1 destination port number
    • 13.3.10 TRUNK0_HASH2 � Trunk group 0 hash result 2 destination port number
    • 13.3.11 TRUNK0_HASH3 � Trunk group 0 hash result 3 destination port number
    • 13.3.12 Trunk Group 1 - Up to four 10/100 ports can be selected for trunk group 1.
    • 13.3.13 TRUNK1_L � Trunk group 1 Low (Managed mode only)
    • 13.3.14 TRUNK1_M � Trunk group 1 Medium (Managed mode only)
    • 13.3.15 TRUNK1_H � Trunk group 1 High (Managed mode only)
    • 13.3.16 TRUNK1_MODE � Trunk group 1 mode
    • 13.3.17 TRUNK1_HASH0 � Trunk group 1 hash result 0 destination port number
    • 13.3.18 TRUNK1_HASH1 � Trunk group 1 hash result 1 destination port number
    • 13.3.19 TRUNK1_HASH2 � Trunk group 1 hash result 2 destination port number
    • 13.3.20 TRUNK1_HASH3 � Trunk group 1 hash result 3 destination port number
    • 13.3.21 Multicast Hash Registers
      • 13.3.21.1 Multicast_HASH0-0 � Multicast hash result 0 mask byte 0
      • 13.3.21.2 Multicast_HASH0-1 � Multicast hash result 0 mask byte 1
      • 13.3.21.3 Multicast_HASH0-2 � Multicast hash result 0 mask byte 2
      • 13.3.21.4 Multicast_HASH0-3 � Multicast hash result 0 mask byte 3
      • 13.3.21.5 Multicast_HASH1-0 � Multicast hash result 1 mask byte 0
      • 13.3.21.6 Multicast_HASH1-1 � Multicast hash result 1 mask byte 1
      • 13.3.21.7 Multicast_HASH1-2 � Multicast hash result 1 mask byte 2
      • 13.3.21.8 Multicast_HASH1-3 � Multicast hash result 1 mask byte 3
      • 13.3.21.9 Multicast_HASH2-0 � Multicast hash result 2 mask byte 0
      • 13.3.21.10 Multicast_HASH2-1 � Multicast hash result 2 mask byte 1
      • 13.3.21.11 Multicast_HASH2-2 � Multicast hash result 2 mask byte 2
      • 13.3.21.12 Multicast_HASH2-3 � Multicast hash result 2 mask byte 3
      • 13.3.21.13 Multicast_HASH3-0 � Multicast hash result 3 mask byte 0
      • 13.3.21.14 Multicast_HASH3-1 � Multicast hash result 3 mask byte 1
      • 13.3.21.15 Multicast_HASH3-2 � Multicast hash result 3 mask byte 2
      • 13.3.21.16 Multicast_HASH3-3 � Multicast hash result 3 mask byte 3
  • 13.4 Group 3 Address CPU Port Configuration Group
    • 13.4.1 MAC0 � CPU Mac address byte 0
    • 13.4.2 MAC1 � CPU Mac address byte 1
    • 13.4.3 MAC2 � CPU Mac address byte 2
    • 13.4.4 MAC3 � CPU Mac address byte 3
    • 13.4.5 MAC4 � CPU Mac address byte 4
    • 13.4.6 MAC5 � CPU Mac address byte 5
    • 13.4.7 INT_MASK0 � Interrupt Mask 0
    • 13.4.8 INTP_MASK0 � Interrupt Mask for MAC Port 0,1
    • 13.4.9 INTP_MASK1 � Interrupt Mask for MAC Port 2,3
    • 13.4.10 INTP_MASK2 � Interrupt Mask for MAC Port 4,5
    • 13.4.11 INTP_MASK3 � Interrupt Mask for MAC Port 6,7
    • 13.4.12 INTP_MASK4 � Interrupt Mask for MAC Port 8,9
    • 13.4.13 INTP_MASK5 � Interrupt Mask for MAC Port 10,11
    • 13.4.14 INTP_MASK6 � Interrupt Mask for MAC Port 12,13
    • 13.4.15 INTP_MASK7 � Interrupt Mask for MAC Port 14,15
    • 13.4.16 INTP_MASK8 � Interrupt Mask for MAC Port 16,17
    • 13.4.17 INTP_MASK9 � Interrupt Mask for MAC Port 18,19
    • 13.4.18 INTP_MASK10 � Interrupt Mask for MAC Port 20,21
    • 13.4.19 INTP_MASK11 � Interrupt Mask for MAC Port 22,23
    • 13.4.20 RQS � Receive Queue Select CPU Address:h323)
    • 13.4.21 RQSS � Receive Queue Status
    • 13.4.22 TX_AGE � Tx Queue Aging timer
  • 13.5 Group 4 Address Search Engine Group
    • 13.5.1 AGETIME_LOW � MAC address aging time Low
    • 13.5.2 AGETIME_HIGH �MAC address aging time High
    • 13.5.3 V_AGETIME � VLAN to Port aging time
    • 13.5.4 SE_OPMODE � Search Engine Operation Mode
    • 13.5.5 SCAN � SCAN Control Register (default 00)
  • 13.6 Group 5 Address Buffer Control/QOS Group
    • 13.6.1 FCBAT � FCB Aging Timer
    • 13.6.2 QOSC � QOS Control
    • 13.6.3 FCR � Flooding Control Register
    • 13.6.4 AVPML � VLAN Tag Priority Map
    • 13.6.5 AVPMM � VLAN Priority Map
    • 13.6.6 AVPMH � VLAN Priority Map
    • 13.6.7 TOSPML � TOS Priority Map
    • 13.6.8 TOSPMM � TOS Priority Map
    • 13.6.9 TOSPMH � TOS Priority Map
    • 13.6.10 AVDM � VLAN Discard Map
    • 13.6.11 TOSDML � TOS Discard Map
    • 13.6.12 BMRC - Broadcast/Multicast Rate Control
    • 13.6.13 UCC � Unicast Congestion Control
    • 13.6.14 MCC � Multicast Congestion Control
    • 13.6.15 PR100 � Port Reservation for 10/100 ports
    • 13.6.16 SFCB � Share FCB Size
    • 13.6.17 C2RS � Class 2 Reserve Size
    • 13.6.18 C3RS � Class 3 Reserve Size
    • 13.6.19 C4RS � Class 4 Reserve Size
    • 13.6.20 C5RS � Class 5 Reserve Size
    • 13.6.21 C6RS � Class 6 Reserve Size
    • 13.6.22 C7RS � Class 7 Reserve Size
    • 13.6.23 QOSCn - Classes Byte Limit Set 0
    • 13.6.24 Classes Byte Limit Set 1
    • 13.6.25 Classes Byte Limit Set 2
    • 13.6.26 Classes Byte Limit Set 3
    • 13.6.27 Classes WFQ Credit Set 0
    • 13.6.28 Classes WFQ Credit Set 1
    • 13.6.29 Classes WFQ Credit Set 2
    • 13.6.30 Classes WFQ Credit Set 3
    • 13.6.31 RDRC0 � WRED Rate Control 0
    • 13.6.32 RDRC1 � WRED Rate Control 1
    • 13.6.33 User Defined Logical Ports and Well Known Ports
    • 13.6.34 USER_PORT0_(0~7) � User Define Logical Port (0~7)
    • 13.6.35 USER_PORT_[1:0]_PRIORITY - User Define Logic Port 1 and 0 Priority
      • 13.6.35.1 USER_PORT_[3:2]_PRIORITY - User Define Logic Port 3 and 2 Priority
      • 13.6.35.2 USER_PORT_[5:4]_PRIORITY - User Define Logic Port 5 and 4 Priority
      • 13.6.35.3 USER_PORT_[7:6]_PRIORITY - User Define Logic Port 7 and 6 Priority
      • 13.6.35.4 USER_PORT_ENABLE[7:0] � User Define Logic 7 to 0 Port Enables
      • 13.6.35.5 WELL_KNOWN_PORT[1:0] PRIORITY- Well Known Logic Port 1 and 0 Priority
      • 13.6.35.6 WELL_KNOWN_PORT[3:2] PRIORITY- Well Known Logic Port 3 and 2 Priority
      • 13.6.35.7 WELL_KNOWN_PORT [5:4] PRIORITY- Well Known Logic Port 5 and 4 Priority
      • 13.6.35.8 WELL_KNOWN_PORT [7:6] PRIORITY- Well Known Logic Port 7 and 6 Priority
      • 13.6.35.9 WELL KNOWN_PORT_ENABLE [7:0] � Well Known Logic 7 to 0 Port Enables
      • 13.6.35.10 RLOWL � User Define Range Low Bit 7:0
      • 13.6.35.11 RLOWH � User Define Range Low Bit 15:8
      • 13.6.35.12 RHIGHL � User Define Range High Bit 7:0
      • 13.6.35.13 RHIGHH � User Define Range High Bit 15:8
      • 13.6.35.14 RPRIORITY � User Define Range Priority
    • 13.6.36 CPUQOSC123
  • 13.7 Group 6 Address MISC Group
    • 13.7.1 MII_OP0 � MII Register Option 0
    • 13.7.2 MII_OP1 � MII Register Option 1
    • 13.7.3 FEN � Feature Register
    • 13.7.4 MIIC0 � MII Command Register 0
    • 13.7.5 MIIC1 � MII Command Register 1
    • 13.7.6 MIIC2 � MII Command Register 2
    • 13.7.7 MIIC3 � MII Command Register 3
    • 13.7.8 MIID0 � MII Data Register 0
    • 13.7.9 MIID1 � MII Data Register 1
    • 13.7.10 LED Mode � LED Control
    • 13.7.11 DEVICE Mode
    • 13.7.12 CHECKSUM - EEPROM Checksum
  • 13.8 (Group 7 Address) Port Mirroring Group
    • 13.8.1 MIRROR1_SRC � Port Mirror source port
    • 13.8.2 MIRROR1_DEST � Port Mirror destination
    • 13.8.3 MIRROR2_SRC � Port Mirror source port
    • 13.8.4 MIRROR2_DEST � Port Mirror destination
  • 13.9 (Group F Address) CPU Access Group
    • 13.9.1 GCR-Global Control Register
    • 13.9.2 DCR-Device Status and Signature Register
    • 13.9.3 DCR1-Chip Status
    • 13.9.4 DPST � Device Port Status Register
    • 13.9.5 DTST � Data read back register
    • 13.9.6 PLLCR - PLL Control Register
    • 13.9.7 LCLK - LA_CLK delay from internal OE_CLK
    • 13.9.8 OECLK - Internal OE_CLK delay from SCLK
    • 13.9.9 DA � DA Register
• 14.0 BGA and Ball Signal Descriptions
  • 14.1 BGA Views (Top-View)
    • 14.1.1 Encapsulated view in unmanaged mode
    • 14.1.2 Encapsulated view in managed mode
  • 14.2 Ball � Signal Descriptions in Managed Mode
    • 14.2.1 Ball Signal Descriptions in Managed Mode
    • 14.2.2 Ball � Signal Descriptions in Unmanaged Mode
  • 14.3 Ball � Signal Name in Unmanaged Mode
  • 14.4 Ball � Signal Name in Managed Mode
  • 14.5 AC/DC Timing
    • 14.5.1 Absolute Maximum Ratings
    • 14.5.2 DC Electrical Characteristics
    • 14.5.3 Recommended Operating Conditions
    • 14.5.4 Typical Reset & Bootstrap Timing Diagram
      • Figure 14 - Typical Reset & Bootstrap Timing Diagram
      • Table 10 - Reset & Bootstrap Timing
    • 14.5.5 Typical CPU Timing Diagram for a CPU Write Cycle
      • Figure 15 - Typical CPU Timing Diagram for a CPU Write Cycle
    • 14.5.6 Typical CPU Timing Diagram for a CPU Read Cycle
      • Figure 16 - Typical CPU Timing Diagram for a CPU Read Cycle
  • 14.6 Local Frame Buffer SBRAM Memory Interface
    • 14.6.1 Local SBRAM Memory Interface
      • Figure 17 - Local Memory Interface � Input Setup and Hold Timing
      • Figure 18 - Local Memory Interface � Output Valid Delay Timing
      • Table 11 - AC Characteristics - Local Frame Buffer SBRAM Memory Interface
  • 14.7 AC Characteristics
    • 14.7.1 Reduced Media Independent Interface
      • Figure 19 - AC Characteristics - Reduce Media Independent Interface
      • Figure 20 - AC Characteristics � Reduced Media Independent Interface
      • Table 12 - AC Characteristics - Reduced Media Independent Interface
    • 14.7.2 LED Interface
      • Figure 21 - AC Characteristics � LED Interface
      • Table 13 - AC Characteristics - LED Interface
    • 14.7.3 SCANLINK SCANCOL Output Delay Timing
      • Figure 22 - SCANLINK SCANCOL Output Delay Timing
      • Figure 23 - SCANLINK, SCANCOL Setup Timing
      • Table 14 - SCANLINK, SCANCOL Timing
    • 14.7.4 MDIO Input Setup and Hold Timing
      • Figure 24 - MDIO Input Setup and Hold Timing
      • Figure 25 - MDIO Output Delay Timing
      • Table 15 - MDIO Timing
    • 14.7.5 I�C Input Setup Timing
      • Figure 26 - I�C Input Setup Timing
      • Figure 27 - I�C Output Delay Timing
      • Table 16 - I�C Timing
    • 14.7.6 Serial Interface Setup Timing
      • Figure 28 - Serial Interface Setup Timing
      • Figure 29 - Serial Interface Output Delay Timing
      • Table 17 - Serial Interface Timing