THIS DOCUMENT IS FOR MAINTENANCE
PURPOSES ONLY AND IS NOT
RECOMMENDED FOR NEW DESIGNS
NJ88C25
The NJ88C25 is a synthesiser circuit fabricated on the GPS
CMOS process and is capable of achieving high sideband
attenuation and low noise performance. It contains a reference
oscillator, 11-bit programmable reference divider, digital and
sample-and-hold comparators, 10-bit programmable `M' counter,
7-bit programmable `A' counter, latched and buffered Band 0 and
Band 1 outputs and the necessary control and latch circuitry for
accepting and latching the input data.
Data is presented serially under external control from a suitable
microprocessor. Although 30 bits of data are initially required to
program all counters, subsequent updating can be abbreviated to
19 bits, when only the `A', `M' and `B' counters require changing.
The NJ88C25 is intended to be used in conjunction with a two-
modulus prescaler such as the SP8710 series to produce a
universal binary coded synthesiser.
Fig.1 Pin connections - top view
FEATURES
s
Low Power Consumption
s
High Performance Sample and Hold Phase Detector
s
Serial Input with Fast Update Feature
DG18, DP18, MP18
ORDERING INFORMATION
NJ88C25 KA DG Ceramic DIL Package
NJ88C25 KA DP Plastic DIL Package
NJ88C25 KA MP Miniature Plastic DIL Package
OSC IN
OSC OUT
DATA
ENABLE
CLOCK
BAND 0
BAND 1
F
IN
V
DD
V
SS
REFERENCE COUNTER
(11BITS)
LATCH 6
LATCH 7
LATCH 8
LATCH 1
LATCH 2
LATCH 3
`M' COUNTER
(10 BITS)
`M' REGISTER
`R' REGISTER
CONTROL LOGIC
LATCH 4
LATCH 5
`A' COUNTER
(7 BITS)
`A' REGISTER
4
2
SAMPLE/HOLD
PHASE
DETECTOR
FREQUENCY/
PHASE
DETECTOR
V
SS
PDA
PDB
LOCK DETECT (LD)
F
V
MODULUS
CONTROL
OUTPUT (MC)
1
2
4
3
16
RB CAP CH
17 15 18
f
r
f
V
`B' REGISTER
LATCH 6
9
10
12
14
13
8
11
5
7
6
V
SS
Fig.2 Block diagram
NJ88C25
FREQUENCY SYNTHESISER (MICROPROCESSOR SERIAL INTERFACE)
CH
RB
MC
CAP
ENABLE
CLOCK
DATA
BAND 1
OSC OUT
PDA
PDB
F
V
LD
F
IN
V
SS
V
DD
BAND 0
OSC IN
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
NJ88C25
DS3280-1.3
ABSOLUTE MAXIMUM RATINGS
Supply voltage, V
DD
2V
SS
:
Input voltage
Open drain output, pins 3 and 4:
All other pins:
Storage temperature:
205V to 7V
7V
V
SS
203V to V
DD
103V
265
C to
1150
C (DG package)
255
C to 1125
C
(DP and MP packages)
NJ88C25 IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS
NJ88C25
Characteristic
Units
Conditions
Min.
Typ.
Max.
Supply current
55
mA
f
osc
, f
F
IN
= 20MHz
07
mA
f
osc
, f
F
IN
= 1MHz
37
mA
f
osc
, f
F
IN
= 10MHz
OUTPUTS
Modulus Control (MC), BAND 1 and BAND 2
High level
V
DD
204
V
I
SOURCE
= 1mA
Low level
04
V
I
SINK
= 1mA
Lock Detect (LD) and F
V
Low level
04
V
I
SINK
= 4mA
Open drain pull-up voltage
70
V
PDB
High level
46
V
I
SOURCE
= 4mA
Low level
04
V
I
SINK
= 4mA
3-state leakage current
01
A
2
ELECTRICAL CHARACTERISTICS AT V
DD
= 5V
Test conditions unless otherwise stated:
V
DD
V
SS
=27V to 55V. Temperature range = 30
C to +70
C
DC Characteristics
Value
Characteristic
Units
Conditions
Min.
Typ.
Max.
F
IN
and OSC IN input level
200
mV RMS 10MHz AC-coupled sinewave
Max. operating frequency, f
F
IN
and f
osc
20
MHz
Input squarewave V
DD
to V
SS
,
Propagation delay, clock to modulus control MC
30
50
ns
See note 2
Programming Inputs
Clock high time, t
CH
05
s
Clock low time, t
CL
05
s
Enable set-up time, t
ES
(see note 5)
02
t
CH
s
Enable hold time, t
EH
02
s
Data set-up time, t
DS
02
s
Data hold time, t
DH
02
s
Clock rise and fall times
02
s
Positive threshold
3
V
TTL compatible, see note 1
Negative threshold
2
V
Phase Detector
Digital phase detector propagation delay
500
ns
Gain programming resistor, RB
5
k
Hold capacitor, CH
1
nF
See note 3
Programming capacitor, CAP
1
nF
Output resistance, PDA
5
k
Value
AC
Characteristics
0 to 5V
square
wave
All timing periods
are referenced to
the negative
transition of the
clock waveform.
See note 5
NOTES
1. Data inputs have internal pull-up resistors to enable them to be driven from TTL outputs.
2. All counters have outputs directly synchronous with their respective clock rising edges.
3. The finite output resistance of the internal voltage follower and `on' resistance of the sample switch driving this pin will add a finite time constant
to the loop. An external 1nF hold capacitor will give a maximum time constant of 5
s.
4. The inputs to the device should be at logic `0' when power is applied if latch-up conditions are to be avoided. This includes the OSC IN and
F
IN
inputs.
5. Clock to enable set-up time (t
ES
) is variable, dependent on f
OSC
. It needs to be specified in terms of f
OSC
, clock high time (t
CH
) and clock low time
(t
CL
) and must meet the following conditions: 431/f
OSC
<t
ES
,(t
CH
1t
CL
).
NJ88C25
PIN DESCRIPTIONS
Description
Analog output from the sample and hold phase comparator for use as a `fine' error signal. Voltage
increases as f
v
(the output from the `M' counter) phase lead increases; voltage decreases as f
r
(the
output from the reference counter) phase lead increases. Output is linear over only a narrow phase
window, determined by gain (programmed by RB). In a type 2 loop, this pin is at (V
DD
2V
SS
)/2 when the
system is in lock.
Three-state output from the phase/frequency detector for use as a `coarse' error signal.
f
v
. f
r
or f
v
leading: positive pulses with respect to the bias point V
BIAS
f
v
, f
r
or f
r
leading: negative pulses with respect to the bias point V
BIAS
f
v
= f
r
and phase error within PDA window: high impedance.
This pin is an open drain output from the `M' counter.
An open-drain lock detect output at low level when phase error is within PDA window (in lock); high
impedance at all other times.
The input to the main counters. It is normally driven from a prescaler, which may be AC-coupled or,
when a full logic swing is available, may be DC-coupled.
Negative supply (ground).
Positive supply (normally 5V)
These pins form an on-chip reference oscillator when a series resonant crystal is connected across
them. Capacitors of appropriate value are also required between each end of the crystal and ground
to provide the necessary additional phase shift. The addition of a 220
resistor between OSC OUT and
the crystal will improve stability. An external reference signal may, alternatively, be applied to OSC IN.
This may be a low-level signal, AC-coupled, or if a full logic swing is available it may be DC-coupled.
The program range of the reference counter is 3 to 2047 , with the total division ratio being twice the
programmed number.
Two latch outputs, providing an output of the data from the `B' register.
Information on this input is transferred to the internal data latches during the appropriate data read time
slot. DATA is high for a `1' and low for a `0'. There are four data words which control the NJ88C25; MSB
is first in the order: `A' (7 bits), `M' (10 bits), ]B' (2 bits) and `R' (11 bits).
Data is clocked on the negative transition of the CLOCK waveform. If less than 30 negative clock
transitions have been received when the ENABLE line goes low (i.e., only `B',`M' and `A' will have been
clocked in), then the `R' counter latch will remain unchanged and only `M' and `A' will be transferred from
the input shift register to the counter latches. This will protect the `R' counter from being corrupted by
any glitches on the clock line after only `B', `M' and `A' have been loaded. If 30 negative transitions have
been counted, then the `R' counter will be loaded with the new data.
When ENABLE is low, the DATA and CLOCK inputs are disabled internally. As soon as ENABLE is
high, the DATA and CLOCK inputs are enabled and data may be clocked into the device. The data is
transferred from the input shift register to the counter latches on the negative transition of the ENABLE
input and both inputs to the phase detector are synchronised to each other.
This pin allows an external capacitor to be connected in parallel with the internal ramp capacitor and
allows further programming of the device. (This capacitor is connected from CAP to V
SS
).
Modulus control output for controlling an external dual-modulus prescaler. MC will be low at the beginning
of a count cycle and will remain low until the `A' counter completes its cycle. MC then goes high and
remains high until the `M' counter completes its cycle, at which point both `A' and `M' counters are reset.
This gives a total division ratio of
MP1A, where P and P11 represent the dual-modulus prescaler
values. The program range of the `A' counter is 0-127 and therefore can control prescalers with a
division ratio up to and including 4128/129. The programming range of the `M' counter is 8-1023
and, for correct operation,
M>A. Where every possible channel is required, the minimum total division
ratio
N should be: N>P
2
2
P.
An external sample and hold phase comparator gain programming resistor should be connected
between this pin and V
SS
.
An external hold capacitor should be connected between this pin and V
SS
.
3
Pin no.
Name
PDA
PDB
F
V
LD
F
IN
V
SS
V
DD
OSC IN/
OSC OUT
BAND 0/1
DATA
CLOCK
ENABLE
CAP
MC
RB
CH
1
2
3
4
5
6
7
9,10
8, 11
12
13
14
15
16
17
18
NJ88C25
Fig. 3 Typical supply current v. input frequency
Fig. 4 Typical supply current v. input level, OSC IN
f
osc
23
fcomp
PROGRAMMING
Reference Divider Chain
The comparison frequency depends upon the crystal
oscillator frequency and the division ratio of th `R' counter,
which can be programmed in the range 3 to 2047, and a fixed
divide by two stage.
where
fosc
=
oscillator frequency,
fcomp
= comparison frequency,
R = `R' counter ratio
For example, where the crystal frequency = 10MHz and a
channel spacing comparison frequency of 125kHz is required,
10
7
23125310
3
Thus, the `R' register would be programmed to 400 expressed
in binary. The total division ratio would then be 23400 = 800
since the total division ratio of the `R' counter plus the 42 stage
is from 6 to 4094 in steps of 2.
VCO Divider Chain
The synthesised frequency of the voltage controlled oscillator
(VCO) will depend on the division ratios of the `M' and `A'
counters, the ratio of the external two-modulus prescaler
(
P/P11)and the comparison frequency .
R =
R =
= 400
Fig. 5 Timing diagram showing timing periods required for correct operation
t
EH
t
EH
t
ES
t
DH
t
ES
t
DS
t
CH
t
CL
CLOCK
ENABLE
DATA
4
N =
= 22310
3
N =
V
DD
= 5V
OSC IN, F
IN
= 0V TO 5V SQUARE WAVE
F
IN
OSC IN
INPUT FREQUENCY (MHz)
1 2 3 4 5 6 7 8 9 10
SUPPLY CURRENT (mA)
20
15
10
05
TOTAL SUPPLY CURRENT IS
THE SUM OF THAT DUE TO
F
IN
AND OSC IN
INPUT LEVEL (V RMS)
02 04 06 08 10 12 14 16
SUPPLY CURRENT (mA)
8
7
6
5
4
3
2
1
V
DD
= 5V
F
IN
= LOW FREQUENCY
0V TO 5V SQUARE WAVE
1MHz
10MHz
22
3
10
3
64
=
M1
The division ratio
N = MP1A,
where
M is the ratio of the `M' counter in the range 8 to 1023
and
A is the ratio of the `A' counter in the range 0 to 127.
Note that
M>A and
f
VCO
fcomp
For example, if the desired VCO frequency = 275MHz, the
comparison frequency is 125kHz and a two-modulus prescaler
of 464/65 is being used, then
275310
6
125310
3
Now,
N = MP1A, which can be rearranged as N/P = M1A/P.
In our example we have
P = 64, therefore
such that
M = 343 and A /64 = 075.
Now,
M is programmed to the integer part = 343 and A is
programmed to the fractional part364 i.e.,
A = 075364 = 48.
NB The minimum ratio
N that can be used is P
2
2
P (=4032 in
our example) for all contiguous channels to be available.
To check:
N = 343364148 = 22000, which is the required
division ratio and is greater than 4032 ( =
P
2
2
P ).
A
64
NJ88C25
5
Fig.6 Timing diagram showing programming details
sample and hold phase detector window, when PDB becomes
high impedance. Phase-lock is indicated at this point by a low
level on LD. The sample and hold phase detector provides a
`fine' error signal to give further phase adjustment and to hold
the loop in lock. An internally generated ramp, controlled by the
digital output from both the reference and main divider chains,
is sampled at the reference frequency to give the `fine' error
signal, PDA. When in phase lock, this output would be typically
at (V
DD
2V
SS
)/2 and any offset from this would be proportional
to phase error.
The relationship between this offset and the phase error is
the phase comparator gain,
K
PDA
, which is programmable with
an external resistor, RB, and a capacitor, CAP. An internal
50pF capacitor is used in the sample and hold comparator.
PHASE COMPARATORS
Noise output from a synthesiser loop is related to loop gain:
K
PD
K
VCO
N
where
K
PD
is the phase detector constant (volts/rad),
K
VCO
is
the VCO constant (rad/sec/volt) and
N is the overall loop division
ratio. When
N is large and the loop gain is low, noise may be
reduced by employing a phase comparator with a high gain.
The sample and hold phase comparator in the NJ88C25 has
a high gain and uses a double sampling technique to reduce
spurious outputs to a low level.
A standard digital phase/frequency detector driving a three-
state output,PDB, provides a `coarse' error signal to enable
fast switching between channels.
The PDB output is active until the phase error is within the
1
2
3
4
5
(17)28
(18)29
(19)30
A
6
A
5
A
4
A
3
A
2
(M
2
)R
2
(B
1
)R
1
(B
0
)R
0
CLOCK
ENABLE
DATA
NJ88C25
HEADQUARTERS OPERATIONS
GEC PLESSEY SEMICONDUCTORS
Cheney Manor, Swindon,
Wiltshire SN2 2QW, United Kingdom.
Tel: (0793) 518000
Fax: (0793) 518411
GEC PLESSEY SEMICONDUCTORS
P.O. Box 660017
1500 Green Hills Road,
Scotts Valley, California 95067-0017,
United States of America.
Tel: (408) 438 2900
Fax: (408) 438 5576
CUSTOMER SERVICE CENTRES
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Fax : (1) 64 46 06 07
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ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993
JAPAN Tokyo Tel: (03) 3296-0281 Fax: (03) 3296-0228
NORTH AMERICA Integrated Circuits and Microwave Products Scotts Valley, USA
Tel (408) 438 2900 Fax: (408) 438 7023.
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Fax: (516) 293 0061.
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Swindon Tel: (0793) 518510 Tx: 444410 Fax : (0793) 518582
These are supported by Agents and Distributors in major countries world-wide.
GEC Plessey Semiconductors 1992 Publication No. DS3280 Issue No. 1.3 May 1992
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded
as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company
reserves the right to alter without prior knowledge the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information
and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury
or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.
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capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
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2
C Standard Specification as defined by Philips.
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