ZIF600

The ZIF600 synthesiser is for channel selection in 4FSK

pagers. A reference frequency is generated by an on-chip
crystal oscillator with an AFC external trimming varacator
controlled by a DAC.

The ZIF600 digital demodulator uses DSP techniques to

optimise the data extraction in the presence of noise and also
generates an AFC output to adjust the crystal frequency.

Separate power controls allow the system current

consumption to be minimised. All functions are controlled by a
serial bus with a simple programming format and with four
control pins which are used to control the power up and power
down functions of the blocks to allow sequenced wake up and
optimised power consumption.

FEATURES

Low Voltage Operation, 2.7 to 3.3V

On-chip Reference Oscillator

Channel Select Synthesiser

Direct VCO input at up to 330MHz

6400 Baud Digital 4FSK Demodulator

Serial Control Bus

Very Low Power Consumption

Small QSOP24 Package

Fig.1 Pin connections - top view

QP24

APPLICATIONS

Pagers - including small form factor designs such as
credit card pagers, watch pagers and PCMCIA
applications

Low data rate receivers - security/remote control

ABSOLUTE MAXIMUM RATINGS

To be defined.

Fig.2 ZIF600 block diagram

ZIF600

RXQ

RXI

SRF

DATA0

DATA1

VSSD

VDDD

VREF

RBIAS

PDOUT

PLLC

DACOUT

DSC2

DSC1

DATA

CLOCK

VSSA

VCOFIN

VDDA

REFOSCB

TSS

REFOSC

VSSI

RXI

RXQ

PHASE

DETECTOR

CONTROL LOGIC &

POWER MANAGEMENT

DSC2

DATA1

REFOSC

REFOSB

VCOFIN

DATA

CLOCK

VDDA

VDDD

TSS

VSSA

PLLC

SRF

VSSI

BIASES

VREF

RBIAS

DATA

SLICER

AFC

(DAC)

DIGITAL DEMODULATOR

REFERENCE

DIVIDER

M AND A

DIVIDERS

DSC1

DACOUT

PDOUT

DATA0

TWO MODULUS

PRESCALER

VSSD

LIMI

LIMQ

Demod. Clock

ZIF600

Pager Synthesiser and 4FSK Demodulator

DS4771 - 1.2 October 1997

ZIF600

TARGET ELECTRICAL CHARACTERISTICS

These characteristics are guaranteed over the following conditions (unless otherwise stated):

VDDD, VDDA = 2.7 TO 3.3V, VDD1 = 0.95V to 1.6V (connected to REFOSCB via ext. resistor) and T

amb

= --20 to + 70

�

Characteristic

Min.

Typ.

Max.

Units

Conditions

Supply current at VDDD,VDDA = 3V

Synthesiser locked and
demodulator active. VDD1

Supply current at VDD1 = 1.4V

350

�

connected to REFOSCB
via external resistor.

VREF bias voltage input range

1.15

1.25

1.31

Logic input HIGH, pins DATA, CLOCK,

VDD - 0.3

VDD + 0.3

LE, DSC1, DSC2, PLLC, SRF, RXI, RXQ

Logic input HIGH, pins DATA, CLOCK,

VSS - 0.3

VSS + 0.3

LE, DSC1, DSC2, PLLC, SRF, RXI, RXQ

Input capacitance (signal pins)

Pin voltage: VSS to VDD

Input leakage (signal pins)

�

Pin voltage: VSS to VDD

Control bus CLOCK frequency

MHz

Synthesiser charge pump output

Pin voltage:

leakage, pin PDOUT

VSS to VDD

Synthesiser charge pump output

160

200

240

�

Pin VDD/2

current, pin PDOUT

Charge pump output compliance

VSS + 0.4

VDD -- 0.4

Current within 10% of its

range, pin PDOUT

value at VDD/2

Main synthesiser input frequency on

330

MHz

VCOFIN

VCOFIN input level

300

1000

pk - pk

Reference Frequency Crystal

12.8

MHz

Pins REFOSC and

14.4

REFOSCB

Logic output HIGH, pins DATA0,

VDD -- 0.3

VDD

Output current, IoH =

DATA1

100

�

Logic output LOW, pins DATA0,

VSS

VSS -- 0.3

Output current, IoL =

DATA1

100

�

Trim DAC output voltage, pin DACOUT

2.375

Not tested Output current
100nA VREF = 1.25V

RXI, RXQ pull-up current

1.5

�

VDD -- 0.3V

RXI, RXQ pull-up current

�

VSS + 0.3V

Input leakage (signal) pins with

�

Pin voltage: VSS to VDD

pull-downs

pins include SRF, PLLC
DSC1, DSC2

ZIF600

FUNCTIONAL DESCRIPTION

The ZIF600 synthesiser is used to select the channel in

4FSK paging receivers and uses on-chip constant current
charge pumps to drive an external passive loop filter. Common
low cost reference crystals are used, at frequencies of 12.8 or
14.4MHz, and are divided to give the required 12.5, 20 or
25kHz channel spacings. The reference crystal oscillator uses
external trimming to meet system requirements and is controlled
by a DAC set by the digital demodulator.

The digital demodulator takes the limited I and Q signals

from the radio receiver and converts the 4-level FSK into 2 bit
data output on pins DATA0 and DATA1. An AFC output from
this demodulator is also included.

Functions are controlled by a serial bus with a simple

programming format and with four control pins to allow optimum
power up sequences which help minimise the system current
consumption.

DESCRIPTION OF FUNCTIONS

Pin No.

Pin Name

Pin Type

Description

RXQ

Receiver "Quadrature" output

RXI

Receiver "In Phase" output

SRF

Symbol Rate Filter

DATA0

Out

Data output to decoder

DATA1

Out

Data output to decoder

VSSD

Digital Ground

VDDD

2.7 to 3.3V Digital Power Supply

VREF

1.25 Volt Reference from ZIF100

RBIAS

Bias setting Resistor 120k

to VSSA max. parasitic capacitance = 5pF

PDOUT

Out

Charge pump output from synthesiser

PLLC

Synthesiser power down

DACOUT

Out

Trim DAC for crystal

VSS1

Ground (substrate)

REFOSC

I/O

Reference Oscillator

TSS

Test Scan Select, Normally logic 0

REFOSCB

I/O

Reference Oscillator. External resistor to VDD1

VDDA

2.7 to 3.3V Analog Power Supply

VCOFIN

VCO frequency input to synthesiser

VSSA

Analog Ground

CLOCK

Control Bus Clock

Control Bus Latch Enable

DATA

Control Bus Data

DSC1

With DSC2 controls the operating mode of the demodulator

DSC2

With DSC1 controls the operating mode of the demodulator

Table 1. List of pins

REFERENCE DIVIDERS

The reference frequency generated by the oscillator on

pins REFOSC and REFOSCB is divided to give the comparison
frequency clock. See Fig. 3.

Ratio selection is five control bits RD1 (where LOW gives

�

8 mode), RD2 (where LOW gives

�

4 mode) and RD3 (where

LOW gives

�

2 mode) which can be set to give the 8 options

needed to get 10kHz, 12.5kHz, 20kHz or 25kHz from either a
12.8 or 14.4MHz crystal, as in Table 2. The additional control
bits RD4 and RD5 allow the option of further division to allow
for an off chip frequency multiplier. If both RD4 and RD5 are set
low then this division stage is bypassed. Other settings for RD4
and RD5 offer division by 2, 3 or 4. Table 3 shows the additional
division options available from RD4 and RD5.

Power down options are available for both the synthesiser

and demodulator, however the crystal oscillator and the
reference divider must be kept running to give a timing signal
to the demodulator whilst the demodulator is on.

Table 2 Reference divider ratios

Crystal

Comp.

Total

RD1

RD2

RD3

MHz

freq. kHz division

12.8

512

14.4

576

12.8

640

14.4

720

12.8

12.5

1024

14.4

12.5

1152

12.8

1280

14.4

1440

Table 3 Additional divider ratios

Additional division

RD4

RD5

Bypass

ZIF600

SYNTHESISER

The Synthesiser divides the VCOFIN frequency by the 16-

bit number FCH programmed from the serial bus and then the
phase detector compares the result with the comparison
frequency signal to generate correction pulses. The division
ratio range is 4,032 to 65,535.

An embedded two modulus prescaler is used to minimise

power consumption but its programming is arranged to be
transparent to the user.

By using a digital phase and frequency detector the loop will

pull in over an unlimited range and then by using a reset signal
fed back from the output current drivers any delays in the
output path do not give a dead band in the phase response.

The charge pump currents are set by internal biasing. The

current level fixed by the circuit has been selected to give
minimum loop disturbance from external interference, while
also not taking excessive current from the supply line. It is
expected that adequate high frequency decoupling will be
provided on the power supplies to eliminate any significant
noise.

Powering up the synthesiser requires that VREF, IBIAS

and PLLC have been turned on for an adequate time before the
synthesiser is required to be functioning.

As the demodulator takes its clock from the synthesiser

reference divider, the synthesiser reference oscillator and
divider circuits must be on and have settled before the
demodulator is turned on.

Setting the "DMO" bit in the control bus allows the main

parts of the synthesiser to be kept in a low power mode with
only the reference oscillator and reference divider operating,
when PLLC is high. This effectively allows the demodulator to
be used standalone with its required clock being provided by
the reference oscillator/divider.

Fig.4 Basic block diagram of synthesiser

"DMO" bit

PLLC

Synthesiser Mode

Synthesiser off

Synthesiser on

Reference oscillator and divider on, remainder of synthesiser circuitry off

Table 4. Synthesiser mode control

16 BIT DIVIDER

CHARGE
PUMP

PDOUT

PHASE

DETECTOR

FCH FROM BUS (16 bit)

RESET

COMPARISON FREQUENCY

(FROM REFERENCE DIVIDER)

VCOFIN

DOWN

Fig.3 Reference divider configuration

�

8/9

RD1

�

4/5

RD2

�

2/4

RD3

�

1/2/3/4

RD4

RD5

CRYSTAL FREQUENCY

12�8 or 14�4 MHz

COMPARISON

FREQUENCY

200 kHz CLOCK TO DEMODULATOR

ZIF600

Fig.5 Response of DATA0 and DATA1 to a

�

4.8kHz I/Q input

DIGITAL DEMODULATOR

By using digital signal processing techniques it is possible

to get a very robust demodulator for 4-level FSK. The
demodulator produces a digital level depending on the received
frequency. A digital data slicer is used to encode the DATA0
and DATA1 signals. Extra functions are included to give an
AFC signal to the 8 bit Trim DAC for the crystal oscillator. The
DAC output will lag the incoming data, and will require some
external filtering to smooth DAC transitions (it is recommended
to connect a 10

�

F capacitor from DACOUT to Ground).

The demodulator receives "I" and "Q" signals from the

ZIF100. Fig.5 shows the DATA0 and DATA1 response to a 4
level I/Q input at

�

4.8kHz from te ZIF100. Table 5 maps the

input frequency represented by the I/Q demodulator inputs to
the DATA0 and DATA1 outputs.

The decoder will recover the symbol clock and sample the

DATA0 and DATA1 signals at the appropriate time. DATA1 will
have multiple edges during symbol transmissions.

In a typical application the ZIF600 receives real time control

from a decoder interface and provided the decoder with DATA0
and DATA1. Fig.6 illustrates the sequence of applied signals
from the Decoder in a typical application. Note that other
system ICs will require additional contol, and this may affect
the sequencing given.

DATA1

DATA0

Frequency Deviation

+4.8kHz

+1.6kHz

--1.6kHz

--4.8kHz

Table 5. Frequency map for DATA output pins

DSC2

DSC1

Demodulator Mode

Off, Hold Data Slicing and AFC loop values

On, Fast Tracking for Data Slicingand AFC loop

On, Slow Tracking for Data Slicingand AFC loop

Off, Hold applied to Data Slicing and AFC loop values

Table 6. Demodulator mode control

SRF

Symbol Rate

Symbol Rate Filter 1600sps

Symbol Rate Filter 3200sps

Table 7. Symbol rate filter control

I (4.8KHz)

DATA0

DATA1

Symbol Transitions

Jitter

Typical Sampling Point

ZIF600

Fig.6 Control signal timing diagram for ZIF600 receiving data

Previous Signal

BS1

"A" -> Frame

Info

Sync 2

Block 0

Block 10

Next Signal

Off

Hold

Slow Track

Fast

Track

PLL Settle

Off

Signal

ZIF 600

Mode

VREF

PLLC

DSC1

DSC2

SRF

1.25v

45mS

20mS

70mS

25mS

1�76 Sec.

VREF On

XTAL On

Synth. On

Demod. Off

Fast Track On

SRF=1600

Demod. On

Synth.On

Fast AFC On

Slow Track On

SRF=1600 or 3200

Demod. On

Synth.On

Slow AFC On

Hold Track

SRF=1600/3200

Demod. On

Synth.On

Hold AFC

SRF=1600

Demod. Off

Synth.On

Hold AFC

All

Off

All

Off

CONTROL BUS

The ZIF600 has its synthesiser and demodulator configured

by a three wire control bus (CLOCK, DATA, LE). The ZIF600
must have these commands applied to it before it can be used.
Each command must be complete. Data is clocked into the
ZIF600 on the rising edg of the clock. Data is latched into the
internal registers when ENABLE is high. Since the ENABLE pin
gives a direct load and also resets some circuits, there will be
a phase discontinuity if data is loaded after the synthesser has
settled. The bus clock does not need to run between messages
and to minimise interference to radio receiver circuits it is
recommended that the clock is stopped whenever it is not
needed. Fig. 7 shows the format of the control bus.

Fig.7 Control bus waveforms

Control bus timing (provisional)

tpw

tse

tpe

20nS

50nS

20nS

50nS

CLOCK

DATA

tpw

tse

tpe

B15

CLOCK

DATA

ADD

ZIF600

PROGRAMMING FORMAT (PRELIMINARY)

Time Order First......

...Last

Bit No. (B)

ADD

Synthesiser

FCH "0"

"0"

System Set-up "0"

"0"

DMO RD5 RD4 RD3 RD2 RD1

"0"

"1"

Table 8. Programming format

Within each field parameters are ordered MSB first and

thenin descending order. Data is retained by ZIF600 until
VDDD is removed.

Name

Length

Meaning

FCH

16 bit word

Synthesiser programmable divider ratio

RD5 -> RD1

5 Bits

programming word to set crystal reference division ratio

DMO

Demodulator only operation. Set to "1" to power up only the reference oscillator and divider
with "PLLC" pin, generating demod. clock & leaving the remainder of PLL in power down.

Table 9. Control bus bit definitions

APPLICATIONS INFORMATION

By using constant current charge pumps the synthesiser

loop filter is purely passive. See Fig.8.

It is recommended that the primary filter is placed as close

to the synthesiser circuit as possible to minimise interference
caused by charge pump current pulses. The high frequency
clean-up filter, if needed at all, can be placed nearer the VCO
as required for board layout.

Suggested component values for

kHz comparison

frequency with a 5MHz/volt VCO are:

R1 = 15k

C1 = 220nF

CP = 18nF

RF = 47k

CF = 1.8nF

To VCO

PDOUT

PRELIMINARY

FILTER

Fig.8 Typical synthesiser loop filter

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Электронный компонент: ZIF600