Document Outline

• Features
• Applications
• Description
  • Figure 1 - Functional Block Diagram
• Changes Summary
• Pinout Diagram (as viewed through top of package)
• 1.0 Device Overview
• 2.0 Functional Description
• 3.0 Frame Alignment Timing
  • Figure 2 - CT-Bus Timing for 8Mbps Backplane Data Streams
  • Figure 3 - ST-BUS Timing for 16Mbps Backplane Data Streams
• 4.0 Switching Configuration
  • 4.1 Backplane Interface
    • Table 1 - Mode Selection for Backplane Streams
  • 4.2 Local Interface
    • Table 2 - Mode Selection for Local LSTio0 - 3 Streams, Group 0
    • Table 3 - Mode Selection for Local LSTio4 - 7 Streams, Group 1
    • Table 4 - Mode Selection for Local LSTio8 - 11 Streams, Group 2
    • Table 5 - Mode Selection for Local LSTio12 - 15 Streams, Group 3
• 5.0 Local Input Delay Selection
• 6.0 Output Advancement Selection
• 7.0 Local Output Timing Considerations
• 8.0 Memory Block Programming
  • Figure 4 - Block Programming Data in the Connection Memories
• 9.0 Delay Through the ZL50030
  • 9.1 Variable Delay Mode
  • 9.2 Constant Delay Mode
• 10.0 Microprocessor Interface
  • 10.1 DTA Data Transfer Acknowledgment Pin
• 11.0 Address Mapping of Memories and Registers
  • Table 6 - Address Map For Internal Registers (A13 = 0)
  • Table 7 - Address Map for Memory Locations (A13 = 1)
• 12.0 Backplane Connection Memory
• 13.0 Local Connection Memory
• 14.0 Bit Error Rate Test
• 15.0 DPLL
  • 15.1 ZL50030 Modes of Operation
    • Figure 5 - Typical Timing Control Configuration
    • 15.1.1 Primary Master Mode
    • 15.1.2 Secondary Master Mode
    • 15.1.3 Slave Mode
• 16.0 DPLL Functional Description
  • Figure 6 - DPLL Functional Block Diagram
  • 16.1 Reference Select and Frequency Mode MUX Circuits
  • 16.2 PRI and SEC MUX Circuits
  • 16.3 Frame Select MUX
  • 16.4 CT Clock and Frame Monitor Circuits
  • 16.5 Reference Monitor Circuits
  • 16.6 State Machine Circuit
    • Figure 7 - State Machine Diagram
  • 16.7 Modes of Operation
    • 16.7.1 Normal Mode
    • 16.7.2 Holdover Mode
    • 16.7.3 Freerun Mode
• 17.0 Phase Locked Loop (PLL) Circuit
  • Figure 8 - Block Diagram of the PLL Module
  • 17.1 Skew Control
    • Figure 9 - Skew Control Circuit Diagram
  • 17.2 Maximum Time Interval Error (MTIE)
  • 17.3 Phase Detector
  • 17.4 Phase Offset Adder
  • 17.5 Phase Slope Limiter
  • 17.6 Loop Filter
  • 17.7 Digitally Controlled Oscillator (DCO)
  • 17.8 Divider
  • 17.9 Frequency Select MUX Circuit
• 18.0 Measures of DPLL Performance
  • 18.1 Intrinsic Output Jitter
  • 18.2 Jitter Tolerance
  • 18.3 Jitter Transfer
    • Figure 10 - DPLL Jitter Transfer Function Diagram - wide range of frequencies
    • Figure 11 - Detailed DPLL Jitter Transfer Function Diagram
  • 18.4 Frequency Accuracy
  • 18.5 Holdover Frequency Stability
  • 18.6 Locking Range
  • 18.7 Phase Slope
  • 18.8 Maximum Time Interval Error (MTIE)
  • 18.9 Phase Lock Time
• 19.0 Initialization of the ZL50030
• 20.0 JTAG Support
  • 20.1 Test Access Port (TAP)
  • 20.2 Instruction Register
  • 20.3 Test Data Register
  • 20.4 BSDL
• 21.0 Register Descriptions
  • Table 8 - Control Register (CR) Bits
  • Table 9 - Device Mode Selection (DMS) Register Bits
  • Table 10 - Block Programming Mode (BPM) Register Bits
  • Table 11 - Local Input Bit Delay Registers (LIDR0 to LIDR5) Bits
  • Table 12 - Local Input Bit Delay Programming
  • Figure 12 - Local Input Bit Delay Timing
  • Table 13 - Backplane Output Advancement Registers (BOAR0 to BOAR3) Bit
  • Figure 13 - Example of Backplane Output Advancement Timing
  • Table 14 - Local Output Advancement Registers (LOAR0 to LOAR1) Bits
  • Figure 14 - Local Output Advancement Timing
  • Table 15 - Local Bit Error Rate Input Selection (LBIS) Register Bits
  • Table 16 - Local Bit Error Rate Register (LBERR) Bits
  • Table 17 - Backplane Bit Error Rate Input Selection (BBIS) Register Bits
  • Table 18 - Backplane Bit Error Rate Register (BBERR) Bits
  • Table 19 - DPLL Operation Mode (DOM1) Register Bits
  • Table 20 - DPLL Operation Mode (DOM2) Register Bits
  • Table 21 - ZL50030 Mode Selection - By Programming DOM1 and DOM2 Registers
  • Table 22 - DPLL Output Adjustment (DPOA) Register Bits
  • Table 23 - DPLL House Keeping (DHKR) Register Bits
  • Table 24 - Backplane Connection Memory Bits
  • Table 25 - BSAB and BCAB Bits Usage when Source Stream is from the Local Port
  • Table 26 - BSAB and BCAB Bits Usage when Source Stream is from the Backplane Port
  • Table 27 - Local Connection Memory Bits
  • Table 28 - LSAB and LCAB Bits Usage when Source Stream is from the Backplane Port
  • Table 29 - LSAB and LCAB Bits Usage when Source Stream is from the Local Port
• 22.0 DC/AC Electrical Characteristics
  • Figure 15 - Backplane Frame Pulse Input and Clock Input Timing Diagram
  • Figure 16 - Backplane Frame Pulse Output and Clock Output Timing Diagram (in Primary Master Mode ...
  • Figure 17 - Backplane Frame Pulse Input and Clock Input Timing Diagram
  • Figure 18 - Reference Input Timing Diagram when the input frequency = 8 kHz
  • Figure 19 - Reference Input Timing Diagram when the input frequency = 2.048 MHz
  • Figure 20 - Reference Input Timing Diagram when the input frequency = 1.544Hz
  • Figure 21 - Reference Output Timing Diagram when (DIV1, DIV0) = (0, 0) in DOM2 Register
  • Figure 22 - Reference Output Timing Diagram when (DIV1, DIV0) = (0, 0) in DOM2 Register
  • Figure 23 - Reference Input Timing Diagram when (DIV1, DIV0) = (0, 0) in DOM2 Register
  • Figure 24 - Reference Output Timing Diagram when (DIV1, DIV0) = (1, 0) in DOM2 Register
  • Figure 25 - Reference Output Timing Diagram when (DIV1, DIV0) = (0, 1) in DOM2 Register
  • Figure 26 - Local Clock Timing Diagram when ST_CKo0/1 frequency = 4.096 MHz
  • Figure 27 - Local Clock Timing Diagram when ST_CKo0/1 frequency = 8.192 MHz
  • Figure 28 - Local Clock Timing Diagram when ST_CKo frequency = 16.384 MHz
  • Figure 29 - C1M5o Output Clock Timing Diagram
  • Figure 30 - Backplane Serial Stream Timing when the Data Rate is 8 Mbps
  • Figure 31 - Backplane Serial Stream Timing when the Data Rate is 16 Mbps
  • Figure 32 - Local Serial Stream Output Timing
  • Figure 33 - Local Serial Stream Input Timing
  • Figure 34 - Serial Output and External Control
  • Figure 35 - Serial Output and External Control
  • Figure 36 - Output Driver Enable (ODE)
  • Figure 37 - Motorola Non-Multiplexed Bus Timing
  • Figure 38 - JTAG Test Port Timing Diagram
  • Figure 39 - Reset Pin Timing Diagram
• 23.0 Trademarks