PS019310-0904
PRELIMINARY
Product Specification
eZ80F915050MOD
eZ80F91 Module
ZiLOG Worldwide Headquarters
532 Race Street
San Jose, CA
95126
Telephone: 408.558.8500
Fax: 408.558.8300
www.ZiLOG.com
PS019310-0904
P R E L I M I N A R Y
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o determine whether
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orldwide Headquarters
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95126
T
elephone: 408.558.8500
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products and/or service names mentioned herein may be trademarks of the companies with which
they are associated.
Document Disclaimer
2004
by ZiLOG, Inc.
All rights reserved. Information in this publication concerning the devices,
applications, or technology described is intended to suggest possible uses and may be superseded.
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ASSUME LIABILITY
FOR OR PROVIDE
A
REPRESENT
A
TION OF
ACCURACY
OF
THE INFORMA
TION, DEVICES, OR
TECHNOLOGY
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DOCUMENT
. ZiLOG
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O USE OF INFORMA
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PS019310-0904
P R E L I M I N A R Y
Revision History
eZ80F915050MOD
eZ80F91 Module
Product Specification
iii
Revision History
Each instance in
T
able 1
reflects a change to this document from its previous revi
-
sion.
T
o see more detail, click the appropriate link in the table.
T
able 1.
Revision History of this Document
Date
Revision
Level
Section
Description
Page
#
July 2004
10
Formatted to current publication standards
All
Ethernet PHY and
RJ45 Connector
section
Part number change to AMD MII.
12
Bill of Materials for
the
eZ80F91
Module
Part number change to internal crystal at jumper
location Y3.
22
PS019310-0304
P R E L I M I N A R Y
Table of Contents
eZ80F915050MOD
eZ80F91 Module
Product Specification
iv
T
able of Contents
Revision History
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ii
i
L
ist of Figures
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
v
List of Tables
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
The
eZ80F91 Module
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
Module Features
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
eZ80F91 Controller Features
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
Block Diagram
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
Pin Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
Peripheral Bus Connector
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
I/O Connector
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
Onboard Component Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
Logic-Level I/Os
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
Onboard Battery Backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Ethernet PHY and RJ45 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Ethernet LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Fast Buffer (U10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
IrDA Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Reset Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Serial Interface Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Document Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Change Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Module Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Customer Feedback Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
PS019310-0304
P R E L I M I N A R Y
List of Figures
eZ80F915050MOD
eZ80F91 Module Product Specification
v
List of Figures
Figure 1.
eZ80F91 Module Functional Block Diagram . . . . . . . . . . . . . . . . . . . 3
Figure 2.
eZ80F91 Module Peripheral Bus Connector Pin Configuration--JP1 4
Figure 3.
eZ80F91 Module I/O Connector Pin Configuration--JP2 . . . . . . . . . 8
Figure 4.
Bus Contention Without the eZ80F91 Module Fast Buffer Feature . 15
Figure 5.
Physical Dimensions of the eZ80F91 Module . . . . . . . . . . . . . . . . . 18
Figure 6.
eZ80F91 Module--Top Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 7.
eZ80F91 Module--Bottom Layer . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 8.
eZ80F91 Module Schematic Diagram, #1 of 3--Connectors
and Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 9.
eZ80F91 Module Schematic Diagram, #2 of 3--CPU and PHY . . . 26
Figure 10. eZ80F91 Module Schematic Diagram, #3 of 3--Module Memory . . 27
PS019310-0304
P R E L I M I N A R Y
List of Tables
eZ80F915050MOD
eZ80F91 Module Product Specification
vi
List of Tables
Table 1. Revision History of this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Table 2. eZ80F91 Module Peripheral Bus Connector Pin Identification* . . . . . . . 5
Table 3. eZ80F91 Module I/O Connector Pin Identification* . . . . . . . . . . . . . . . . 8
Table 4. eZ80F91 Ethernet Module MII Resistor Configuration . . . . . . . . . . . . . 12
Table 5. Flash Memory Programming Signals and Jumpers . . . . . . . . . . . . . . . 16
Table 6. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7. Bill of Materials for the eZ80F91 Module . . . . . . . . . . . . . . . . . . . . . . . 22
PS019310-0904
P R E L I M I N A R Y
The eZ80F91 Module
eZ80F915050MOD
eZ80F91 Module Product Specification
1
The eZ80F91 Module
The eZ80F91 Module is a compact, high-performance Ethernet module specially
designed for the rapid development and deployment of embedded systems
requiring control and Internet/Intranet connectivity.
This expandable module is powered by ZiLOG's latest power-efficient, high-
speed, optimized pipeline architecture eZ80F91 microcontroller, a member of
ZILOG's family of eZ80Acclaim! Flash Microcontrollers.
The eZ80F91 is a high-speed single-cycle instruction-fetch microcontroller, which
can operate with a clock speed of 50
MHz. It can operate in Z80-compatible
addressing mode (64
KB) or full 24-bit addressing mode (16
MB).
The rich peripheral set of the eZ80F91 Module makes it suitable for a variety of
applications, including industrial control, IrDA connectivity, communication, secu-
rity, automation, point-of-sale terminals, and embedded networking applications.
Module Features
Factory-default operating clock frequency at 50
MHz
10/100
Base-T Ethernet PHY with RJ45 connector
512
KB fast SRAM
256
KB on-chip Flash memory
1
MB off-chip NOR Flash memory
Battery-backed Real-Time Clock
I/O connector provides 32 general-purpose 5
V-tolerant I/O pinouts
ZiLOG's industry-leading IrDA transceiver--ZiLOG ZHX1810
Onboard connector provides I/O bus for external peripheral connections (IRQ,
CS, 24 address, 8 data)
Low-cost connection to carrier board via two 2x30pin headers
Small footprint 63.5mm x 78.7mm
3.3
V power supply
Standard operating temperature range: 0C to +70C
PS019310-0904
P R E L I M I N A R Y
The eZ80F91 Module
eZ80F915050MOD
eZ80F91 Module Product Specification
2
eZ80F91 Controller Features
The eZ80F91 device contains 256
KB of Flash memory and 8
KB of SRAM
Single-cycle instruction fetch, high-performance, pipelined eZ80
CPU core
10/100 Mbps Ethernet MAC with 8KB frame buffer
Low power features including SLEEP mode, HALT mode, and selective peripher-
al power-down control
Two UARTs with independent baud rate generators and support for 9-bit opera-
tion
SPI with independent clock generator
I
2
C with independent clock generator
Infrared Data Association (IrDA)-compliant infrared encoder/decoder
New DMA-like eZ80
instructions for efficient block data transfer
External interface with 4 chip selects, individual wait state generators, and an ex-
ternal WAIT input pin -- supports Intel- and Motorola-style buses
Flexible-priority vectored interrupts (both internal and external) and interrupt con-
troller
Real-time clock with on-chip 32KHz oscillator, selectable 50/60Hz input, and sep-
arate V
DD
pin for battery backup
Four 16-bit Counter/Timers with prescalers and direct input/output drive
Watch-Dog Timer
32 bits of general-purpose I/O
JTAG and ZDI debug interfaces
144-pin LQFP package
3.03.6
V supply voltage with 5V tolerant inputs
Standard operating temperature range: 0C to +70C
Block Diagram
Figure 1 provides a block diagram of the eZ80F91 Module.
PS019310-0904
P R E L I M I N A R Y
The eZ80F91 Module
eZ80F915050MOD
eZ80F91 Module Product Specification
3
Figure 1. eZ80F91 Module Functional Block Diagram
PS019310-0904
P R E L I M I N A R Y
Pin Description
eZ80F915050MOD
eZ80F91 Module Product Specification
4
Pin Description
Peripheral Bus Connector
Figure 2 illustrates the pin layout of the 60-pin Peripheral Bus Connector (JP1) of
the eZ80F91 Module. The eZ80
Development Platform, however, features a 50-
pin connector. The eZ80F91 Module is designed to interface pin 60 of its JP1 con-
nector to pin 50 of the eZ80
Development Platform's JP1 connector so that pins
110 of the eZ80F91 Module overlap the edge of the eZ80
Development Plat-
form. Table 2 identifies the pins and their functions.
Figure 2. eZ80F91 Module
Peripheral Bus Connector Pin Configuration--JP1
PS019310-0904
P R E L I M I N A R Y
Pin Description
eZ80F915050MOD
eZ80F91 Module Product Specification
5
All signals with an overline are active Low. For example, B/W, for which
WORD is active Low, and B/W, for which BYTE is active Low.
Table 2. eZ80F91 Module Peripheral Bus Connector Pin Identification*
Pin #
Symbol
Pull
Up/Down*
Signal Direction Comments
1
Reserved
2
Reserved
3
Reserved
4
Reserved
5
TRSTN
Input
Reset for On-Chip Instrumentation (OCI).
6
Reserved
7
F91_WE
PU 10
K
Input
A Low enables a Write to on-chip Flash
memory. If this pin is unconnected, on-chip
Flash memory is write-protected.
8
Reserved
9
GND
V
SS
/Ground (0
V).
10
V
CC
3.3
V supply input pin.
11
A6
Bidirectional
12
A0
Bidirectional
13
A10
Bidirectional
14
A3
Bidirectional
15
GND
V
SS
/Ground (0
V).
16
V
CC
3.3
V supply input pin.
17
A8
Bidirectional
18
A7
Bidirectional
19
A13
Bidirectional
20
A9
Bidirectional
21
A15
Bidirectional
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0D7 and A0A23 should be below 10
pF to satisfy
timing requirements for the CPU.
All unused inputs should be pulled to either V
DD
or GND, depending on their inactive levels, to reduce power
consumption and to reduce noise sensitivity.
All inputs are CMOS level 3.3
V (5
V tolerant), except where otherwise noted.
Note:
PS019310-0904
P R E L I M I N A R Y
Pin Description
eZ80F915050MOD
eZ80F91 Module Product Specification
6
22
A14
Bidirectional
23
A18
Bidirectional
24
A16
Bidirectional
25
A19
Bidirectional
26
GND
V
SS
/Ground (0
V).
27
A2
Bidirectional
28
A1
Bidirectional
29
A11
Bidirectional
30
A12
Bidirectional
31
A4
Bidirectional
32
A20
Bidirectional
33
A5
Bidirectional
34
A17
Bidirectional
35
Reserved
36
DIS_Flash
PU 10
K
Input
A Low disables onboard Flash memory.
Flash is enabled if DIS_Flash is not
connected; CMOS Input 3.3
V (5
V tolerant).
37
A21
Bidirectional
38
V
CC
3.3
V supply input pin.
39
A22
Bidirectional
40
A23
Bidirectional
41
CS0
Output
42
CS1
Output
43
CS2
Output
44
D0
PU 4k
Bidirectional
45
D1
PU 4k
Bidirectional
Table 2. eZ80F91 Module Peripheral Bus Connector Pin Identification* (Continued)
Pin #
Symbol
Pull
Up/Down*
Signal Direction Comments
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0D7 and A0A23 should be below 10
pF to satisfy
timing requirements for the CPU.
All unused inputs should be pulled to either V
DD
or GND, depending on their inactive levels, to reduce power
consumption and to reduce noise sensitivity.
All inputs are CMOS level 3.3
V (5
V tolerant), except where otherwise noted.
PS019310-0904
P R E L I M I N A R Y
Pin Description
eZ80F915050MOD
eZ80F91 Module Product Specification
7
I/O Connector
Figure 3 illustrates the pin layout of the 60-pin I/O Connector (JP2) of the eZ80F91
Module. The eZ80
Development Platform, however, features a 50-pin connector.
The eZ80F91 Module is designed to interface pin 60 of its JP2 connector to pin 50
of the eZ80
Development Platform's JP2 connector so that pins 110 of the
eZ80F91 Module overlap the edge of the eZ80
Development Platform. Table 3
identifies the pins and their functions.
46
D2
PU 4k
Bidirectional
47
D3
PU 4k
Bidirectional
48
D4
PU 4k
Bidirectional
49
D5
PU 4k
Bidirectional
50
GND
V
SS
/Ground (0
V).
51
D7
PU 4k
Bidirectional
52
D6
Bidirectional
53
MREQ
Bidirectional
54
IORQ
Bidirectional
55
GND
V
SS
/Ground (0
V).
56
RD
Bidirectional
57
WR
Bidirectional
58
INSTRD
Output
59
BUSACK
Output
60
BUSREQ
PU 2k
Input
Table 2. eZ80F91 Module Peripheral Bus Connector Pin Identification* (Continued)
Pin #
Symbol
Pull
Up/Down*
Signal Direction Comments
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0D7 and A0A23 should be below 10
pF to satisfy
timing requirements for the CPU.
All unused inputs should be pulled to either V
DD
or GND, depending on their inactive levels, to reduce power
consumption and to reduce noise sensitivity.
All inputs are CMOS level 3.3
V (5
V tolerant), except where otherwise noted.
PS019310-0904
P R E L I M I N A R Y
Pin Description
eZ80F915050MOD
eZ80F91 Module Product Specification
8
Figure 3. eZ80F91 Module
I/O Connector Pin Configuration--JP2
Table 3. eZ80F91 Module I/O Connector Pin Identification*
Pin #
Symbol
Pull
Up/Down
Signal
Direction
Comments
1
PA7
Bidirectional
2
PA6
Bidirectional
3
PA5
Bidirectional
4
PA4
Bidirectional
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0D7 and A0A23 should be below 10
pF to satisfy
timing requirements for the CPU.
All unused inputs should be pulled to either V
DD
or GND, depending on their inactive levels, to reduce power
consumption and to reduce noise sensitivity.
All inputs are CMOS level 3.3
V (5
V tolerant), except where otherwise noted.
PS019310-0904
P R E L I M I N A R Y
Pin Description
eZ80F915050MOD
eZ80F91 Module Product Specification
9
5
PA3
Bidirectional
6
PA2
Bidirectional
7
PA1
Bidirectional
8
PA0
Bidirectional
9
V
CC
3.3
V supply input pin.
10
GND
V
SS
/Ground (0
V).
11
PB7
Bidirectional
12
PB6
Bidirectional
13
PB5
Bidirectional
14
PB4
Bidirectional
15
PB3
Bidirectional
16
PB2
Bidirectional
17
PB1
Bidirectional
18
PB0
Bidirectional
19
GND
V
SS
/Ground (0
V).
20
PC7
Bidirectional
21
PC6
Bidirectional
22
PC5
Bidirectional
23
PC4
Bidirectional
24
PC3
Bidirectional
25
PC2
Bidirectional
26
PC1
Bidirectional
27
PC0
Bidirectional
28
PD7
Bidirectional
29
PD6
Bidirectional
Table 3. eZ80F91 Module I/O Connector Pin Identification* (Continued)
Pin #
Symbol
Pull
Up/Down
Signal
Direction
Comments
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0D7 and A0A23 should be below 10
pF to satisfy
timing requirements for the CPU.
All unused inputs should be pulled to either V
DD
or GND, depending on their inactive levels, to reduce power
consumption and to reduce noise sensitivity.
All inputs are CMOS level 3.3
V (5
V tolerant), except where otherwise noted.
PS019310-0904
P R E L I M I N A R Y
Pin Description
eZ80F915050MOD
eZ80F91 Module Product Specification
10
30
GND
V
SS
/Ground (0
V).
31
PD5
Bidirectional
32
PD4
PD 4k
Bidirectional
33
PD3
Bidirectional
34
PD2
Bidirectional
35
PD1
Bidirectional
36
PD0
Bidirectional
37
TDO
Output
JTAG Data Output pin.
38
TDI/ZDA
Input
JTAG Data Input pin.
39
GND
V
SS
/Ground (0
V).
40
TRIGOUT
Output
Active High trigger event indicator.
41
TCK/ZCL
PU 10
K
Input
JTAG Input. High on reset enables ZDI mode; Low on
reset enables OCI debug.
42
TMS
PU 10
K
Input
JTAG Test Mode Select Input.
43
RTC_V
DD
RTC supply. For proper operation of the eZ80F91
Module, this pin must be connected to the same
power source that powers the module (as is done on
the ZiLOG development platform).
44
EZ80CLK
Output
Synchronous CPU clock output.
45
I
2
CSCL
PU 4k
Bidirectional
I
2
C Bus Clock.
46
GND
V
SS
/Ground (0
V).
47
I
2
CSDA
PU 4k
Bidirectional
I
2
C Data Clock.
48
GND
Power
V
SS
/Ground (0
V).
49
FlashWE
PU 10
K
Input
A Low enables a Write to external Flash memory boot
block area. If this pin is unconnected, the Flash
memory boot block area is write-protected.
50
GND
V
SS
/Ground (0
V).
Table 3. eZ80F91 Module I/O Connector Pin Identification* (Continued)
Pin #
Symbol
Pull
Up/Down
Signal
Direction
Comments
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0D7 and A0A23 should be below 10
pF to satisfy
timing requirements for the CPU.
All unused inputs should be pulled to either V
DD
or GND, depending on their inactive levels, to reduce power
consumption and to reduce noise sensitivity.
All inputs are CMOS level 3.3
V (5
V tolerant), except where otherwise noted.
PS019310-0904
P R E L I M I N A R Y
Pin Description
eZ80F915050MOD
eZ80F91 Module Product Specification
11
51
CS3
Output
Used on the eZ80190, eZ80L92, eZ80F92, eZ80F93
devices and connected to the CS8900 EMAC.
52
DIS_IRDA
PU 10
K
Input
A Low disables the onboard IRDA transceiver to use
PC0/PC1 UART pins externally.
53
RESET
PU 2k
Bidirectional
Reset Output from module or push-button reset.
54
WAIT
PU 2k
Input
Driving the WAIT pin Low forces the CPU to provide
additional clock cycles for an external peripheral or
external memory to complete its Read or Write opera-
tion.
55
V
CC
3.3
V supply input pin.
56
GND
V
SS
/Ground (0
V).
57
HALT_SLP
Output, Active
Low
A Low on this pin indicates that the CPU enters either
HALT or SLEEP mode because of execution of either
a HALT or SLP instruction.
58
NMI
PU 10
K
Schmitt Trigger
Input, Active
Low
The NMI input is a higher priority input than the
maskable interrupts. It is always recognized at the
end of an instruction, regardless of the state of the
interrupt enable control bits. This input includes a
Schmitt trigger to allow RC rise times. This external
NMI signal is combined with an internal NMI signal
generated from the WDT block before being con-
nected to the NMI input of the CPU.
59
V
CC
3.3
V supply input pin.
60
Reserved
NC
Reserved--No Connection.
Table 3. eZ80F91 Module I/O Connector Pin Identification* (Continued)
Pin #
Symbol
Pull
Up/Down
Signal
Direction
Comments
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0D7 and A0A23 should be below 10
pF to satisfy
timing requirements for the CPU.
All unused inputs should be pulled to either V
DD
or GND, depending on their inactive levels, to reduce power
consumption and to reduce noise sensitivity.
All inputs are CMOS level 3.3
V (5
V tolerant), except where otherwise noted.
PS019310-0904
P R E L I M I N A R Y
Onboard Component Description
eZ80F915050MOD
eZ80F91 Module Product Specification
12
Onboard Component Description
Logic-Level I/Os
The I/O connector features 32 general-purpose 3.3
V CMOS I/O pins that can be
used as outputs or inputs interfacing to external logic. All I/Os are 5
V tolerant.
Some of the General-Purpose I/O pins support dual mode functions (SPI, Timer I/O,
UARTs and bit I/O with edge- or level-triggered interrupt functions on each pin). For
more information on eZ80F91 dual modes, please refer to the eZ80F91 Product
Specification (PS0192).
Onboard Battery Backup
An onboard Panasonic VL-1220-1VC 3V Lithium battery powers the 32kHz Real-
Time Clock when external power is removed. The battery is charged through
diode CR1 and resistor R28 when external power is applied to the board.
Ethernet PHY and RJ45 Connector
The eZ80F91 Ethernet Module contains Advanced Micro Devices' Am79C874
Media-Independent Interface (MII) and a HALO RJ45 with integrated magnetics
(transformer and common-mode chokes) and two LED indicators.
The MII enables different modes of Ethernet communication, configurable by
resistors R19, R21, R23, and R24. The eZ80F91 Ethernet Module is shipped with
all four resistors installed. Table 4, which lists the available resistor settings, is
excerpted from the Am79C874 data sheet published by AMD.
Table 4. eZ80F91 Ethernet Module MII Resistor Configuration
R24
ANEG
R19
(Tech[2])
R23
(Tech[1])
R21
(Tech[0]) Speed
Full-
Duplex
ANEG-EN Capabilities
ANEG
IN
IN
IN
IN
Yes
1
Yes
1
No
All
Disabled
IN
IN
IN
OUT
No
No
No
10HD
Disabled
IN
IN
OUT
IN
No
No
No
100HD
Disabled
Notes:
1. MII Register 0 (Speed and Duplex Bits) must be set by a MAC to achieve a link.
2. When autonegotiation is enabled, these bits can be written but will be ignored by PHY.
3. The advertised abilities of MII Register 4 cannot exceed the abilities of MII Register 1. Autonegotiation should
always be enabled.
PS019310-0904
P R E L I M I N A R Y
Onboard Component Description
eZ80F915050MOD
eZ80F91 Module Product Specification
13
Ethernet LEDs
The Ethernet connection is provided by the HALO RJ45 connector. It contains two
green LEDs that are located next to each other on the eZ80F91 Module. When
PHY is receiving data, the left LED is on. When the PHY is transmitting data, the
right LED is on.
Fast Buffer (U10)
The eZ80F91 Module's fast buffer (see
Figure 1
on page 3) exists to prevent bus
contention that will occur because of slow turn-off time of the module's external
Flash and the fast bus turn-around time of the eZ80F91 (generic feature of the
eZ80
family when it is used in native mode).
Below is a short explanation of the problem related to bus contention when using
eZ80 family of the microprocessors in native eZ80
mode. Refer to
Figure 4
on
IN
IN
OUT
OUT
No
No
No
100HD
Disabled
IN
OUT
IN
IN
Yes
1
Yes
1
No
All
Disabled
IN
OUT
IN
OUT
No
No
No
10FD
Disabled
IN
OUT
OUT
IN
No
No
No
100FD
Disabled
IN
OUT
OUT
OUT
No
No
No
100FD
Disabled
OUT
IN
IN
IN
Yes
2
Yes
2
Yes
3
None
Enabled
OUT
IN
IN
OUT
Yes
2
Yes
2
Yes
3
10HD
Enabled
OUT
IN
OUT
IN
Yes
2
Yes
2
Yes
3
100HD
Enabled
OUT
IN
OUT
OUT
Yes
2
Yes
2
Yes
3
100HD, 10HD
Enabled
OUT
OUT
IN
IN
Yes
2
Yes
2
Yes
3
None
Enabled
OUT
OUT
IN
OUT
Yes
2
Yes
2
Yes
3
10FD/HD
Enabled
OUT
OUT
OUT
IN
Yes
2
Yes
2
Yes
3
100FD/HD
Enabled
OUT
OUT
OUT
OUT
Yes
3
Yes
2
Yes
3
All
Enabled
Table 4. eZ80F91 Ethernet Module MII Resistor Configuration (Continued)
R24
ANEG
R19
(Tech[2])
R23
(Tech[1])
R21
(Tech[0]) Speed
Full-
Duplex
ANEG-EN Capabilities
ANEG
Notes:
1. MII Register 0 (Speed and Duplex Bits) must be set by a MAC to achieve a link.
2. When autonegotiation is enabled, these bits can be written but will be ignored by PHY.
3. The advertised abilities of MII Register 4 cannot exceed the abilities of MII Register 1. Autonegotiation should
always be enabled.
PS019310-0904
P R E L I M I N A R Y
Onboard Component Description
eZ80F915050MOD
eZ80F91 Module Product Specification
14
page 15 while reading the following discussion. Also see the eZ80F91 Product
Specification (PS0192) for further details.
Bus contention occurs when two or more devices drive a common bus. The
eZ80F91's CS0 drives the Flash CE. After the access to Flash, CS0 is driven High
a maximum of 8.8
ns after the next rising edge of the Clock (T6,
Figure 4
). The
Flash turn-off time (T
OD
) is 25
ns, which is the time from OE or CE going High to
the Flash output drivers going into High-Z mode. In other words, after the end of
the eZ80F91 Read access to Flash, it takes 8.8
ns+25
ns = 33.8
ns before Flash
stops driving the data bus. At this point, the eZ80F91 device is already well into
the next bus cycle.
Assume that the next cycle is Memory Write. During the Memory Write cycle, Data
(output) from the eZ80F91 device is valid not later than T3 = 7.5
ns, and the Write
pulse is asserted not later than 4.5
ns after the falling edge of the Clock (14.5
ns
from the Rising edge if Clock is 50
MHz). It means that during T
CON
= (33.8
ns
7.5
ns) = 26.3
ns; two devices drive the common Data Bus--the eZ80F91 device
and Flash. In turn, data that is being written during the Write operation might be
corrupted. The part used to isolate a slow Flash data bus from a fast eZ80F91 bus
has 5.5
ns turn-off time, which reduces 25
ns part of the T
CON
to 5.5
ns. As a result,
bus contention still occurs, but its duration is not 26.3
ns, as the following equation
shows:
Time of contention = (8.8
ns - 7.5
ns + 5.5
ns) = 6.8
ns
Data being written is not corrupted because the Write pulse is not yet asserted.
PS019310-0904
P R E L I M I N A R Y
Onboard Component Description
eZ80F915050MOD
eZ80F91 Module Product Specification
15
Memory
The eZ80F91 Module contains external Flash memory, and the eZ80F91 MCU
contains internal Flash memory. To allow Read/Write access to Flash memory on
the eZ80F91 Module, there are two signals provided, on connectors JP1 and JP2.
A jumper JP3 on the module enables programming of on-chip Flash.
There is also a signal that duplicates the function of this jumper. Table 5 describes
the states of the signals and the status of the jumper for different modes.
Figure 4. Bus Contention Without the eZ80F91 Module Fast Buffer Feature
PS019310-0904
P R E L I M I N A R Y
Onboard Component Description
eZ80F915050MOD
eZ80F91 Module Product Specification
16
The eZ80F91 Module's external Flash memory has an access time of 100
ns. At
least five wait states must be added to the cycle when accessing external Flash at
the 50MHz clock speed. eZ80F91 MCU on-chip Flash is faster; its minimum
access time is 60
ns, which requires only three wait states at 50
MHz.
There is 512
KB of fast SRAM on the eZ80F91 Module. Access time is 12
ns,
which requires one wait-state access. The eZ80F91 on-chip SRAM can be used
with zero wait states.
IrDA Transceiver
An onboard IrDA transceiver (ZiLOG ZHX1810) is connected to PD0 (TX), PD1
(RX), and PD2 (Shutdown, R_SD). The IrDA transceiver is of the LED type
870
nm Class 1.
The receiver supply current is 90150
A and the transmitter supply current is
260
mA when the LED is active.The IrDA transceiver is accessible via the IrDA
controller attached to UART0 on the eZ80F91 device. The UART0 console and
the IrDA transceiver cannot be used simultaneously.
To use the UART0 for console or to save power, the transceiver can be disabled
by the software or by an off-board signal when using the proper jumper selection.
The transceiver is disabled by setting PD2 (IR_SD) High or by pulling the
DIS_IRDA pin on the I/O connector Low. The shutdown is used for power savings.
To enable the IrDA transceiver, DIS_IRDA is left floating and PD2 is set to Low.
Reset Generator
The onboard Reset Generator Chip performs reliable Power-On Reset. The chip
generates a reset pulse with a duration of 200
ms if the power supply drops below
Table 5. Flash Memory Programming Signals and Jumpers
Signal/Jumper
Function
State/Status
DIS_FLASH
Controls Read/Write access to eZ80F91 Module external Flash
memory
When Low, access
is enabled
FlashWE
Controls Write operations to the boot block of eZ80F91 Module
external Flash memory
When Low, Write is
enabled
JP3
Controls Write access to eZ80F91 MCU on-chip Flash memory
When IN, Write is
enabled
F91_WE
Controls Write access to eZ80F91 MCU on-chip Flash memory
When Low, Write is
enabled
PS019310-0904
P R E L I M I N A R Y
Onboard Component Description
eZ80F915050MOD
eZ80F91 Module Product Specification
17
2.93
V. This reset pulse ensures that the board always starts in a defined condi-
tion. The RESET pin on the I/O connector reflects the status of the RESET line. It
is a bidirectional pin for resetting external peripheral components or for resetting
the eZ80F91 Module with a low-impedance output (e.g. a 100-Ohm pushbutton).
Serial Interface Ports
The CPU contains two UARTs with programmable baud rate generators. UART0
is connected to GPIO PD[0:7] on the I/O connector. UART1 is connected to GPIO
PC[0:7] on the I/O connector.
Do not connect an RS-232 interface without level shifters. There are no
RS232-level shifters on the eZ80F91 Module.
Physical Dimensions
The footprint of the eZ80F91 Module PCB is 63.5
mm
x
78.7
cm. With an RJ-45
Ethernet connector, the overall height is 25
mm. See Figure 5.
Note:
PS019310-0904
P R E L I M I N A R Y
Onboard Component Description
eZ80F915050MOD
eZ80F91 Module Product Specification
18
Figure 5. Physical Dimensions of the eZ80F91 Module
JP1
1
JP2
1
Y3
P2
CR1
U6
C1
C11
C12
C18
C19
C20
C21
C22
C3
C40
C42
R10
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R28
R29
R3
R36
R37
R4
R6
U5
U8
U3
Y2
Y1
U4
U2
U1
VL1
+
JP3
ISO
COPYRIGHT ZiLOG XTOOLS 2002
ZiLOG PCA: 99C0879-001
eZ80F91 MODULE
2
78.7 mm
31.8 mm
56.0 mm
16.5 mm
63.5 mm
PS019310-0904
P R E L I M I N A R Y
Onboard Component Description
eZ80F915050MOD
eZ80F91 Module Product Specification
19
Figure 6 illustrates the top layer silkscreen of the eZ80F91 Module.
Figure 6. eZ80F91 Module--Top Layer
JP1
1
JP2
1
Y3
P2
CR1
U6
C1
C11
C12
C18
C19
C20
C21
C22
C3
C40
C42
R10
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R28
R29
R3
R36
R37
R4
R6
U5
U8
U3
Y2
Y1
U4
U2
U1
VL1
+
JP3
ISO
COPYRIGHT ZiLOG XTOOLS 2002
ZiLOG PCA: 99C0879-001
eZ80F91 MODULE
2
PS019310-0904
P R E L I M I N A R Y
Onboard Component Description
eZ80F915050MOD
eZ80F91 Module Product Specification
20
Figure 7 illustrates the bottom layer silkscreen of the eZ80F91 Module.
Absolute Maximum Ratings
Stresses greater than those listed in Table 6 can cause permanent damage to the
device. These ratings are stress ratings only. Operation of the device at any con-
dition outside those indicated in the operational sections of these specifications is
not implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect device reliability. For improved reliability, unused inputs should be
tied to one of the supply voltages (V
DD
or V
SS
).
Figure 7. eZ80F91 Module--Bottom Layer
Table 6. Absolute Maximum Ratings
Parameter
Min
Max
Units
Standard operating temperature
0
+70
C
Storage temperature
45
+85
C
Operating Humidity (RH @ 50C)
25%
90%
Operating Voltage
--
3.6
V
L1
R9
C10
C13
C14
C15
C16
C17
C2
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C4
C41
C43
C44
C45
C46
C47
C48
C49
C5
C50
C51
C52
C53
C6
C7
C8
C9
R1
R11
R12
R2
R26
R27
R30
R31
R32
R33
R34
R35
R5
R7
R8
U9
U10
MADE IN U.S.A.
ZiLOG FAB: 98C0879-001 REV A
1
DJP 2002
JP2
JP1
2
PS019310-0904
P R E L I M I N A R Y
Document Number Description
eZ80F915050MOD
eZ80F91 Module Product Specification
21
Document Number Description
The Document Control Number that appears in the footer of each page of this
document contains unique identifying attributes, as indicated in the following
table:
Change Log
PS
Product Specification
0193
Unique Document Number
10
Revision Number
0904
Month and Year Published
Rev
Date
Purpose
01
December 2002
Original issue
02
January 2003
Minor content revision
03
February 2003
Minor content revision
04
June 2003
Minor content revision
05
June 2003
Minor content revision
06
August 2003
Hyperlink correction
07
December 2003
Typo correction
08
December 2003
Correction to BOM
09
March 2004
Correction to schematic
10
September 2004 Corrections to PHY section
PS019310-0904
P R E L I M I N A R Y
Document Number Description
eZ80F915050MOD
eZ80F91 Module Product Specification
22
Module Bill of Materials
Table 7 lists the installed components of the eZ80F91 Module.
Table 7. Bill of Materials for the eZ80F91 Module
Part Number
Part Name
Qty.
Jumper
Location Manufacturer
98C0879-001
Fab, eZ80F91 Module, Rev. B
1
--
Prime Technologies
35-0180-12
IC, SRAM, 512Kx8, 12ns, 3V, 36-SOJ
1
U8
Alliance Semi.
AS7C34096-12JC
35-0016-05
IC, 74LVC04, 3.3V, GATE, 14-SOIC
1
U1
Texas Instruments
SN74LVC04AD
35-0720-10
IC, Flash, 1Mx8, 100ns, 3V, 40-TSSOP
1
U9
Micron Technologies
MT28F008B3VG-10B
35-0719-00
IC, MAX6328, RESET, SOT-23
1
U3
Maxim Inc.
MAX6328UR29-T
ZHX1810
IC, IR Transceiver, Low Profile
1
U2
ZiLOG Inc.
ZHX1810MV115THTR
35-0062-01
IC, 74LCX32, LV, QUAD OR, 14-TSSOP
1
U4
Fairchild Semi.
74LCX32MTC
35-0022-01
IC, AM7C874, PHY XCVR, 80QFP
1
U6
AMD AM79C874VC
eZ80F91
IC, eZ80F91, 50MHZ, 144VQFP
1
U5
ZiLOG Inc. eZ80F91
35-0731-00
IC, 74CBTLV3861PWR, 24-TSSOP
1
U10
Texas Instruments
SN74CBTLV3861PWR
48-1013-01
Diode, TVS Array, XCVR Prot, 8-SOIC
1
U9
Semtec
LCDA15C-6
17-2005-70
CAP, 1000
pF, 50
V, Ceramic Chip, 0603
15
C13, C14,
C31-43
Panasonic
ECJ-1VC1H561J
17-2005-66
CAP, 0.1
F, 16
V, Ceramic Chip, 0603
28
C2,10,
C15-30,
C44-53
Kemet Inc.
C0603C104K5RAC
17-2005-54
CAP, 0.01
F, 50
V, Ceramic Chip, 0603
1
C3
Panasonic
ECJ-1VB1C103K
17-2005-83
CAP, 0.33
F, 16
V, Ceramic Chip, 0603
1
C1
Panasonic
ECJ-1VF1C334Z
17-2005-63
CAP, 560
pF, 50
V, Ceramic Chip, 0603
1
C6
Panasonic
ECJ-1VC1H563K
PS019310-0904
P R E L I M I N A R Y
Document Number Description
eZ80F915050MOD
eZ80F91 Module Product Specification
23
17-2001-03
CAP, 12
pF, 50
V, Ceramic Chip, 0603
4
C9, C11,
C12
Panasonic
ECJ-1VC1H120J
17-2001-05
CAP, 22PF, 50V, CER CHIP, 0603
2
C4, C7
PANASONIC
ECJ-1VC1H220J
17-2001-20
CAP, 270PF, 50V, CER CHIP, 0603
1
C5
PANASONIC
ECJ-1VC1H271J
17-2001-01
CAP, 5PF, 50V, CER CHIP, 0603
1
C8
PANASONIC
ECJ-1VC1H050C
48-0051-00
DIODE, 1N5817, RCTFR
1
CR1
MOTOROLA
1N5817
16-9005-33
INDUCTOR, 3.3
H, 20%, 1210 SMD
1
L1
PANASONIC
ELJ-PA3R3MF
46-3001-03
Resistor, 10
K, 1%, 1/16
W, 0603 SMT
15
R3, 8, 10,
R12-18,
R20, 25,
29, 30, 37
Sprague
420CK472X2PD
46-3000-00
Resistor, 0
, 1%, 1/16
W, 0603 SMT
4
R19, 21,
23, 24
"
46-3000-71
Resistor, 2.21
K, 1%, 1/16W, 0603 SMT
2
R5, R6
"
46-3000-35
Resistor, 68
, 1%, 1/16
W, 0603 SMT
1
R3
"
46-3000-02
RES, 2.2
, 1%, 1/16W, 0603 SMT
1
R4
"
46-3000-32
RES, 49.9
, 1%, 1/16W, 0603 SMT
4
R11, 31,
32, 33
"
46-3000-63
RES, 1
K, 1%, 1/16W, 0603 SMT
1
R22
"
46-3000-56
RES, 499
,1%, 1/16W, 0603 SMT
1
R26
"
46-3001-34
RES, 200
K, 1%, 1/16W, 0603 SMT
1
R27
"
46-3000-47
RES, 221
, 1%, 1/16W, 0603 SMT
1
R28
"
46-3000-51
RES, 332
, 1%, 1/16W, 0603 SMT
2
R34, R35 "
46-3001-75
RES, 10
M, 1%, 1/16W, 0603 SMT
1
R38
"
23-0000-25
XTAL, 25.0000
MHz, SER/RESN, HC49S
1
Y1
CITIZEN
HC49US25.000MABJ
23-0000-50
XTAL, 50.0000
MHz, SER/RESN, HC49S
1
Y2
CITIZEN
HC49US50.000MABJ
Table 7. Bill of Materials for the eZ80F91 Module (Continued)
Part Number
Part Name
Qty.
Jumper
Location Manufacturer
PS019310-0904
P R E L I M I N A R Y
Document Number Description
eZ80F915050MOD
eZ80F91 Module Product Specification
24
23-0006-00
Internal crystal, 32.768
KHz, SER/RESN,
TF case
1
Y3
Fox NC-38
21-0907-01
Connector, RJ45, Fast jack,10/100 Base-T
1
P2
Halo Electronics
HFJ11-2450E-L11
21-0055-02
Connector, HDR/PIN, .025SQ, double row
2
JP1, JP2
(backside)
Harwin
M-20-976-3622
Table 7. Bill of Materials for the eZ80F91 Module (Continued)
Part Number
Part Name
Qty.
Jumper
Location Manufacturer
PS019310-0904
P R E L I M I N A R Y
Schematics
eZ80F915050MOD
eZ80F91 Module
Product Specification
25
Schematics
Figures 8 through
10
diagram the layout of the
eZ80F91 Module
. Ethernet circuiting devices are not loaded on the
eZ80F91 Module
. However
, these devices appear in the following schematics for reference purposes.
Figure 8.
eZ80F91 Module
Schematic Diagram, #1 of 3--Connectors and Miscellaneous
Connector 2
Connector 1
=
(MMA 02 04)
open-drain
alternative: Maxim MAX6802UR29D3
WR_EN
D3
PD1
-RD
-BUSREQ
-BUSREQ
GND
TDO
D[0..7]
A8
-CS0
-DIS_FLASH
-RESET
A22
-WR
RTC_VDD
-BUSACK
A[0..23]
PD3
-WR
-HALT_SLP
-MREQ
A19
A13
-FLASHWE
A10
D5
-RESET
-WAIT
-WAIT
TDO
GND
PD5
PB1
-NMI
-IOREQ
A5
PD6
-MREQ
D7
-CS[0..3]
A11
-CS2
-FLASHWE
PB[0..7]
A15
A18
A2
PB3
IICSDA
PC2
-INSTRD
PC6
GND
-BUSACK
PC[0..7]
TMS
D1
A4
TCK
PB5
-HALT_SLP
PC4
IICSCL
TCK
PC0
IICSCL
A21
PD[0..7]
GND
TRIGOUT
TDI
A6
PB7
-CS3
RTC_VDD
IICSDA
CLK_OUT
EZ80CLK
IICSDA
IICSCL
-DIS_IRDA
IR_SD
PD2
DISABLE_IRDA
IRDA_SD
PD0
IRDA_SD
PD1
A17
D2
A16
A1
-BUSREQ
GND
D6
A9
-CS1
A23
-IOREQ
A0
A7
GND
D4
A12
-DIS_FLASH
D0
-INSTRD
-RD
A20
A14
PD7
PD2
PB4
-DIS_IRDA
PD4
TMS
PC5
PB6
EZ80CLK
PD0
PC7
-NMI
PB0
GND
TRIGOUT
-WAIT
PC3
PB2
PC1
GND
TDI
GND
GND
GND
PA7
PA5
PA3
PA1
PA6
PA4
PA2
PA0
-TRSTN
-F91_WE
-F91_WP
-RESET
PA[0..7]
A3
VCC
VCC
VCC
VCC
VCC
VCC
VCC
-TRSTN
-F91_WE
GND
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
GND
GND
VCC
R3
68R
R37
10K
C1
330nF
R12
10K
R6
2.2K
R4
2R7
R2
4.7K
C2
0.1F
U1C
74LCX04
TSSOP14
5
6
C3
0.01F
R20
10K
U1B
74LCX04
TSSOP14
3
4
U1A
74LCX04
TSSOP14
1
2
R5
2.2K
R7
10K
R8
10K
R1
4.7K
U4A
74LCX32
TSSOP14
1
2
3
R9
4.7K
U3
MAX6328UR29
SOT-23-L3
2
1
3
RESET
GND
V
DD
JP2
HEADER 30x2/SM
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
U4D
74LCX32
TSSOP14
12
13
11
U2
ZHX1810
2
4
3
1
5
6
0
TXD
SD
RXD
LEDA
VCC
GND
T
U1F
74LCX04
TSSOP14
13
12
R10
10K
JP1
HEADER 30x2/SM
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
JP3
1
2
U4B
74LCX32
TSSOP14
4
5
6
-BUSACK
TDO
PB[0..7]
-WR
-NMI
-FLASHWE
CLK_OUT
-HALT_SLP
-MREQ
IICSDA
-BUSREQ
-RD
D[0..7]
-INSTRD
GND
PD[0..7]
-DIS_FLASH
-WAIT
IICSCL
-RESET
A[0..23]
-IOREQ
PC[0..7]
-CS[0..3]
RTC_VDD
-F91_WP
TDI
TRIGOUT
TCK
TMS
-TRSTN
PA[0..7]
VCC
PS019310-0904
P R E L I M I N A R Y
Schematics
eZ80F915050MOD
eZ80F91 Module
Product Specification
26
Figure 9.
eZ80F91 Module
Schematic Diagram, #2 of 3--CPU and PHY
Put caps between pairs of U6, 10:11, 51:52, 59:65
and 71:73 as close to the pins as possible
D0
D1
D2
D3
D5
D7
D4
D6
A6
A1
A3
A0
A2
A5
A7
A4
A14
A9
A11
A8
A10
A13
A15
A12
A22
A17
A19
A16
A18
A21
A23
A20
MDC
TXD2
TXD0
TXD3
TXD1
TXER
MDI0
TXEN
PA1
PA6
PA4
PA7
PA5
PA2
PA0
PA3
PB1
PB6
PB4
PB7
PB5
PB2
PB0
PB3
PD1
PD6
PD4
PD7
PD5
PD2
PD0
PD3
TMS
-WAIT
-BUSREQ
TCK
-NMI
-TRSTN
-RESET
TDI
-F91_WP
CRS
RXD0
RXER
RXD3
COL
RXDV
RXD1
RXCLK
RXD2
TXCLK
-CS1
-MREQ
-WR
-IORQ
-RD
-CS0
-CS2
-CS3
SCL
SDA
-RESET
RXD3
RXD0
MDI0
MDC
RXDV
RXD2
RXD1
RXER
TXD3
RXCLK
TXCLK
TXD0
TXER
COL
TXD2
TXD1
TXEN
CRS
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
RTC_VDD
GND
VCC
VCC
VCC
GND
GND
GND
VCC
GND
GND
GND
VCC
VCC
-LEDLNK
-LEDRX
VCC
-LEDRX
-LEDLNK
VCC
GND
VCC
VCC
GND
GND
VCC
P2
HFJ11-2450E-L11
1
4
2
3
5
6
8
9
10
12
11
TX+
TXCT
TX-
RX+
RXCT
RX-
GND
AN1
CT1
CT2
AN2
C10
0.1F
C46
0.1F
C29
0.1F
C28
0.1F
C16
0.1F
C19
0.1F
C51
0.1F
R24
0
C37
0.001F
R18 10K
L1
3.3H
C24
0.1F
R11 49.9
C4
18pF
C6
0.056F
C42
0.001F
R16
10K
C47
0.1F
C30
0.1F
C33
0.001F
C17
0.1F
C20
0.1F
U5
EZ80F91
1
2
3
4
5
8
9
10
11
12
13
16
17
18
19
20
21
24
25
26
27
28
29
30
39
40
41
42
43
44
45
46
54
57
66
67
69
71
56
55
144
49
50
51
52
33
34
35
36
110
109
126
127
128
129
130
132
142
143
124
125
135
137
138
139
140
141
136
131
83
85
86
6
14
22
31
47
59
81
87
88
98
112
122
133
7
15
23
32
38
48
60
64
72
82
84
89
99
108
113
123
134
121
120
119
118
117
116
115
114
107
106
105
104
103
102
101
100
97
96
95
94
93
92
91
90
80
79
78
77
76
75
74
73
65
111
70
68
58
53
63
62
61
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
D0
D1
D2
D3
D4
D5
D6
D7
WAIT
BUSREQ
TMS
TCK
TDI
TRSTN
NMI
RESET
WP
IORQ
MRQ
RD
WR
CS0
CS1
CS2
CS3
SCL
SDA
MII_TXD3
MII_TXD2
MII_TXD1
MII_TXD0
MII_TXEN
MII_TXER
MII_MDC
MII_MDIO
MII_CRS
MII_COL
MII_RXER
MII_RXDV
MII_RXD0
MII_RXD1
MII_RXD2
MII_RXD3
MII_RXCLK
MII_TXCLK
FILT_IN
XOUT
XIN
VDD
VDD
VDD
VDD
VDD
VDD
VDD
PLL_VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PLL_VSS
VSS
VSS
VSS
VSS
VSS
VSS
PA7_PWM3
PA6_PWM2_EC1
PA5_PWM1_TOUT1
PA4_PWM0_TOUT0
PA3_PWM3_OC3
PA2_PWM2_OC2
PA1_PWM1_OC1
PA0_PWM0_OC0
PB7_MOSI
PB6_MISO
PB4_ICB3
PB4_ICA3
PB3_SCK
PB2_SS
PB0_IC1
PB0_IC0_EC0
PC7_RI1
PC6_DCD1
PC5_DSR1
PC4_DTR1
PC3_CTS1
PC2_RTS1
PC1_RXD1
PC0_TXD1
PD7_RI0
PD6_DCD0
PD5_DSR0
PD4_DTR0
PD3_CTS0
PD2_RTS0
PD1_RXD0_IRRXD
PD0_TXD0_IRTXD
HALT_SLP
PHI
TDO
TRIGOUT
BUSACK
INSTRD
RTC_VDD
RTC_XOUT
RTC_XIN
C52
0.1F
C38
0.001F
C25
0.1F
R31 49.9
C7
18pF
C5
220pF
C43
0.001F
C48
0.1F
C31
0.001F
R22 1K
R19
0
C34
0.001F
C21
0.1F
U6
AM79C874
1
2
3
5
7
8
9
14
15
16
17
18
19
20
21
22
30
23
24
25
26
29
31
33
37
38
39
40
34
32
41
42
43
53
54
55
56
72
61
44
45
46
47
48
57
58
62
68
67
66
69
70
74
75
77
78
64
63
4
11
12
28
35
50
51
65
71
76
10
13
27
36
49
52
59
60
73
79
80
PCSB
ISODEF
ISO
REFCLK
BURN_IN
RST
PWRDN
PHYAD4_0RXD-
PHYAD3_10RXD+
PHYAD2_10TXD++
PHYAD1_10TXD-
PHYAD0_10TXD--
GPIO0_10TXD--
GPIO1_TP125
MDIO
MDC
RXCLK
RXD3
RXD2
RXD1
RXD0
RXDV
RXER_RXD4
TXCLK_PCSBPCLK
TXD0
TXD1
TXD2
TXD3
TXEN
TXER_TXD4
COL
CRS
INTR
TECH_SEL2
TECH_SEL1
TECH_SEL0
ANEGA
IBREF
RPTR
LEDSPD0_LEDBTA_FXSEL
LECOL_SCRAMEN
LEDRX_LEDSEL
LEDTX_LEDBTB
LEDLNK_LED_10LNK
LESPD1_LEDTXA_CLK25EN
LEDDPX_LEDTXB
TEST3_SDI+
TEST2
TEST1_FXR+
TEST0_FXR-
FXT+
FXT-
XTL-
XTL+
TX+
TX-
RX+
RX-
TG
ND1
PL
L
G
N
D
OGND1
DGND1
DGND2
OGND2
CRV
GND
EQ
G
N
D
RE
F
G
ND
TG
ND2
PL
L
VC
C
OV
DD1
V
DD1
V
DD2
OV
DD2
CRV
V
CC
AD
O
VC
C
EQ
VC
C
RE
F
V
CC
TV
CC1
TV
CC2
C53
0.1F
R27
200K
C8
5pF
C39
0.001F
R13
10K
C44
0.1F
C26
0.1F
1N5817
CR1
2
1
Y3
32.768KHz
R32
49.9
R17
10K 0.1%
R26
499
R28
220
C49
0.1F
C32
0.001F
R21
0
C35
0.001F
R34
330
C22
0.1F
C11
12pF
C40
0.001F
Y1
25 MHz
R14
10K
C45
0.1F
C27
0.1F
C15
0.1F
C18
0.1F
R33
49.9
R25
10K
R38
10M
Y2
50MHz
C50
0.1F
R23
0
C36
0.001F
VL1
C9
10pF
R35
330
C23
0.1F
C12
12pF
C41
0.001F
R15
10K
-F91_WP
-RESET
-TRSTN
TDI
TCK
TMS
-NMI
-BUSREQ
-WAIT
D[0:7]
PA[0:7]
PC[0:7]
PD[0:7]
PB[0:7]
TRIGOUT
TDO
CLK_OUT
-HALT_SLP
IICSCL
-CS3
-IORQ
-MREQ
-RD
-WR
-CS0
-CS1
-CS2
IICSDA
-BUSACK
-INSTRD
A[0:23]
RTC_VDD
GND
VCC
PS019310-0904
P R E L I M I N A R Y
Schematics
eZ80F915050MOD
eZ80F91 Module
Product Specification
27
Figure 10.
eZ80F91 Module
Schematic Diagram, #3 of 3--Module Memory
D7
D0
A4
A2
A14
A12
A3
D1
D6
A5
A11
-CS1
D5
D2
A6
A18
A7
A10
A0
A17
A13
A16
A9
D3
-RD
A15
-WR
A8
A1
D4
-WP
VCC
-FLASH_EN
-FLASHWE
-CSFLASH
-CS0
A20
A11
DFLASH3
A1
DFLASH0
D6
-RESET
-CSFLASH
A17
A13
A9
D3
D2
A16
A10
DFLASH4
D1
-WR
A12
A2
D5
GND
-RESET
-WR
A4
A0
-RD
A[0..23]
A[0..23]
A21
A18
A8
DFLASH1
D7
A3
-CSFLASH
A14
A7
-CS0
A15
-RD
D4
-WP
DFLASH7
A5
DFLASH5
D0
A19
A6
DFLASH6
DFLASH2
-DIS_FLASH
-CS1
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
R30
10K
C14
0.001F
C13
0.001uF
U9
Flash 1Mx8 3.3V
TSOP40.20MM
MT28F008B3VG
25
21
26
20
27
19
28
18
32
17
33
16
34
15
35
14
8
7
36
6
5
4
3
2
1
40
13
37
38
22
24
9
10
12
11
29
23
39
30
31
DQ0
A0
DQ1
A1
DQ2
A2
DQ3
A3
DQ4
A4
DQ5
A5
DQ6
A6
DQ7
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
N.C.
CE
OE
WE
RP
WP
VPP
N.C.
VSS
VSS
VD
D
VD
D
R29
10K
U10
74CBTLV3384
SO24.300
3
2
4
7
5
8
6
11
14
9
17
18
10
21
15
22
16
19
20
23
1
13
1A1
1B1
1A2
1A3
1B2
1A4
1B3
1A5
2A1
1B4
2A2
2A3
1B5
2A4
2B1
2A5
2B2
2B3
2B4
2B5
1OE
2OE
U1D
74LCX04
TSSOP14
9
8
U1E
74LCX04
TSSOP14
11
10
U8
512KB x 8 SRAM
SOJ36.400
31
35
6
34
5
33
7
32
4
3
24
2
25
23
26
36
29
30
1
22
28
13
27
21
8
11
12
18
17
10
19
20
16
15
14
9
OE
A18
CE
A17
A4
A16
I/O0
A15
A3
A2
A14
A1
I/O4
A13
I/O5
N.C.
I/O6
I/O7
A0
A12
VSS
WE
VDD
A11
I/O1
I/O2
I/O3
A9
A8
VSS
N.C.
A10
A7
A6
A5
VDD
U4C
74LCX32
TSSOP14
9
10
8
D[0:7]
A[0:23]
-RD
-WR
-CS0
-DIS_FLASH
-RESET
-FLASHWE
-CS1
PS019310-0904
P R E L I M I N A R Y
Customer Feedback Form
eZ80F915050MOD
eZ80F91 Module Product Specification
28
Customer Feedback Form
The eZ80F91 Module Product Specification
If you experience any problems while operating this product, or if you note any inaccuracies
while reading this Product Specification, please copy and complete this form, then mail or fax it to
ZiLOG (see Return Information, below). We also welcome your suggestions!
Customer Information
Product Information
Return Information
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ZiLOG Customer Support
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