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Электронный компонент: Z86C93

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1
Z86C93
CPS DC-4020-12
Z86C93
CMOS Z8
M
ULT
/D
IV
M
ICROCONTROLLER
GENERAL DESCRIPTION
C
USTOMER
P
ROCUREMENT
S
PECIFICATION
The Z86C93 is a CMOS ROMless Z8 microcontroller en-
hanced with a hardwired 16-bit x 16-bit multiplier,
32-bit/16-bit divider, and three 16-bit counter timers (see
Functional Block Diagram). A capture register and a fast
decrement mode are also provided. It is offered in 40-pin
PDIP, 44-pin PLCC, 44-pin QFP, and 48-pin VQFP pack-
ages. The Z86C93 is functionally compatible with the
Z86C91, yet it offers a more powerful mathematical capa-
bility. In the PDIP package, the Z86C93 is fully pin compat-
ible with the Z86C91. In the PLCC package, the Z86C93 is
also pin compatible to the Z86C91, with the addition of four
signals (SCLK, /IACK, /SYNC, and /WAIT). The /WAIT
signal is only available on the 25 MHz and 33 MHz devices.
The Z86C93 provides up to 16 output address lines permit-
ting an address space of up to 64 Kbytes of data and
program memory each. Eight address outputs (AD7-AD0)
are provided by a multiplexed, 8-bit, Address/Data bus.
The remaining 8 bits can be provided by the software
configuration of Port 0 to output address bits A15-A8.
There are 256 registers located on chip and organized as
236 general-purpose registers, 16 control and status reg-
isters, one reserved register, and up to three I/O port
registers. The register file can be divided into 16 groups of
16 working registers each. Configuration of the registers in
this manner allows the use of short format instructions; in
addition, any of the individual registers can be accessed
directly. There are an additional 17 registers implemented
in the Expanded Register File in Banks D and E. Two of the
registers may be used as general-purpose registers, while
15 registers supply the data and control functions for the
Multiply/Divide Unit and additional Counter/Timer blocks.
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.:
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection
Circuit
Device
Power
V
CC
V
DD
Ground
GND
V
SS
DC-4020-12
(2-16-94)
2
Z86C93
CPS DC-4020-12
GENERAL DESCRIPTION
(Continued)
Functional Block Diagram
Port 3
UART
32
16
Divider
16 x 16
Multiplier
Port 2
I/O
(Bit Programmable)
ALU
FLAGS
Register
Pointer
Register File
256 x 8-Bit
Program
Counter
4
4
Port 0
Output
Input
Address or I/O
(Nibble Programmable)
8
Port 1
Address/Data
Three 16-Bit
Counter/Timers
VCC GND
Interrupt
Control
Machine Timing, Emulation
and Instruction Control
R//W
/SYNC
XT
AL
/AS
/
DS
/RESET
SCLK
IACK
/W
AIT
(25 MHz & 33 MHz
Devices Only
.)
3
Z86C93
CPS DC-4020-12
40-Pin DIP Package
(20 MHz)
1
2
9
3
4
5
6
7
8
40
39
38
37
36
35
34
33
32
P36
P31
P21
P27
P26
P25
P24
P23
P22
VCC
XTAL2
P37
P30
/RESET
R//W
/DS
31
30
29
28
27
14
10
11
12
13
XTAL1
GND
P32
P00
P01
P20
P33
P34
P17
P16
Z86C93
DIP
15
26
25
24
23
22
21
20
16
17
18
19
/AS
P35
P02
P03
P06
P07
P05
P04
P13
P15
P14
P12
P11
P10
44-Pin PLCC Package
(20 MHz)
7
8
9
10
11
12
13
14
15
16
17
38
37
36
35
34
33
32
31
30
29
39
Z86C93
MCU
6
5
4
3
2
1
44 43 42 41 40
18 19 20 21 22 23 24 25 26 27 28
NC
P24
P23
P22
P21
P20
P33
P34
P17
P16
P15
/SYNC
P14
P13
P12
P11
P10
P07
P06
P05
P04
P03
/RESET
R//W
/DS
/AS
P35
GND
P32
P00
P01
P02
IACK
P25
P26
P27
P31
P36
+5V
XTAL2
XTAL1
P37
P30
SCLK
34
35
36
37
38
39
40
41
42
43
44
21
20
19
18
17
16
15
14
13
12
22
33 32 31 30 29 28 27 26 25 24 23
1
2
3
4
5
6
7
8 9 10 11
Z86C93
MCU
P25
P26
P27
P31
P36
+5V
XTAL2
XTAL1
P37
P30
SCLK
/RESET
R//W
/DS
/AS
P35
GND
P32
P00
P01
P02
IACK
/SYNC
P14
P13
P12
P11
P10
P07
P06
P05
P04
P03
NC
P24
P23
P22
P21
P20
P33
P34
P17
P16
P15
48-Pin VQFP Package
(20 MHz)
44-Pin QFP Package
(20 MHz)
+5V
P37
P30
SCLK
NC
P25
P26
P27
P31
P36
XTAL2
XTAL1
P06
P05
P04
P03
NC
25
NC
37
38
39
40
41
36 35 34 33 32 31 30 29 28 27 26
Z86C93
MCU
43
44
45
46
47
48
2
3
4
5
6
7
8 9 10 11 12
/RESET
R//W
/DS
/AS
P35
GND
P32
P00
P01
P02
IACK
23
22
21
20
19
18
24
/SYNC
P14
P13
P12
P11
P10
P07
13
16
15
14
NC
P24
P23
P22
P21
P20
P33
P34
P17
P16
P15
42
1
NC
17
PIN CONFIGURATION
4
Z86C93
CPS DC-4020-12
PIN CONFIGURATIONS
(Continued)
40-Pin DIP Package
(25 MHz and 33 MHz)
1
2
9
3
4
5
6
7
8
40
39
38
37
36
35
34
33
32
P36
P31
P21
P27
P26
P25
P24
P23
P22
VCC
XTAL2
P37
P30
/RESET
R//W
/DS
31
30
29
28
27
14
10
11
12
13
XTAL1
GND
P32
P00
P01
P20
P33
P34
P17
P16
Z86C93
DIP
15
26
25
24
23
22
21
20
16
17
18
19
/AS
P35
P02
P03
P06
P07
P05
P04
P13
P15
P14
P12
P11
P10
7
8
9
10
11
12
13
14
15
16
17
38
37
36
35
34
33
32
31
30
29
39
Z86C93
MCU
6
5
4
3
2
1
44 43 42 41 40
18 19 20 21 22 23 24 25 26 27 28
/WAIT
P24
P23
P22
P21
P20
P33
P34
P17
P16
P15
/SYNC
P14
P13
P12
P11
P10
P07
P06
P05
P04
P03
/RESET
R//W
/DS
/AS
P35
GND
P32
P00
P01
P02
IACK
P25
P26
P27
P31
P36
+5V
XTAL2
XTAL1
P37
P30
SCLK
34
35
36
37
38
39
40
41
42
43
44
21
20
19
18
17
16
15
14
13
12
22
33 32 31 30 29 28 27 26 25 24 23
1
2
3
4
5
6
7
8 9 10 11
Z86C93
MCU
P25
P26
P27
P31
P36
+5V
XTAL2
XTAL1
P37
P30
SCLK
/RESET
R//W
/DS
/AS
P35
GND
P32
P00
P01
P02
IACK
/SYNC
P14
P13
P12
P11
P10
P07
P06
P05
P04
P03
/WAIT
P24
P23
P22
P21
P20
P33
P34
P17
P16
P15
+5V
P37
P30
SCLK
NC
P25
P26
P27
P31
P36
XTAL2
XTAL1
P06
P05
P04
P03
NC
25
NC
37
38
39
40
41
36 35 34 33 32 31 30 29 28 27 26
Z86C93
MCU
43
44
45
46
47
48
2
3
4
5
6
7
8 9 10 11 12
/RESET
R//W
/DS
/AS
P35
GND
P32
P00
P01
P02
IACK
23
22
21
20
19
18
24
/SYNC
P14
P13
P12
P11
P10
P07
13
16
15
14
/WAIT
P24
P23
P22
P21
P20
P33
P34
P17
P16
P15
42
1
NC
17
44-Pin QFP Package
(25 MHz and 33 MHz)
48-Pin VQFP Package
(25 MHz and 33 MHz)
44-Pin PLCC Package
(25 MHz and 33 MHz)
5
Z86C93
CPS DC-4020-12
Symbol Description
Min
Max
Units
V
CC
Supply Voltage*
0.3
+7.0
V
T
STG
Storage Temp
65
+150
C
T
A
Oper Ambient Temp
C
* Voltages on all pins with respect to GND.
See Ordering Information
Stress greater than those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This
is a stress rating only; operation of the device at any
condition above those indicated in the operational sec-
tions of these specifications is not implied. Exposure to
absolute maximum rating conditions for an extended pe-
riod may affect device reliability.
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to GND.
Positive current flows into the referenced pin (Test Load
Diagram).
ABSOLUTE MAXIMUM RATINGS
V Commutation
DUT
Device Under Test
I
OH
OL
I
50 pf
Test Load Diagram
6
Z86C93
CPS DC-4020-12
DC ELECTRICAL CHARACTERISTICS
VCC = 3.3V
10%
T
A
= 0
C to +70
C
Typical
Sym
Parameter
Min
Max
at 25
C
Units
Conditions
Max Input Voltage
7
V
I
IN
250
A
V
CH
Clock Input High Voltage
0.8 V
CC
V
CC
V
Driven by External Clock Generator
V
CL
Clock Input Low Voltage
0.03
0.1xV
CC
V
Driven by External Clock Generator
V
IH
Input High Voltage
0.7xV
CC
V
CC
V
V
IL
Input Low Voltage
0.3
0.1xV
CC
V
V
OH
Output High Voltge
1.8
V
I
OH
= 1.0 mA
V
OH
Output High Voltage
V
CC
100mV
V
I
OH
= 100
A
V
OL
Output Low Voltage
0.4
V
I
OL
= +1.0 mA
V
RH
Reset Input High Voltage
0.8xV
CC
V
CC
V
V
Rl
Reset Input Low Voltage
-0.03
0.1xV
CC
V
I
IL
Input Leakage
2
2
A
Test at 0V, V
CC
I
OL
Output Leakage
2
2
A
Test at 0V, V
CC
I
IR
Reset Input Current
180
A
V
RL
= 0V
I
CC
Supply Current
30
20
mA
@ 25 MHz [1]
I
CC1
Standby Current (HALT Mode)
12
8
mA
HALT Mode V
IN
= OV, V
CC
@ 25 MHz [1]
I
CC2
Standby Current (HALT Mode)
8
1
A
STOP Mode V
IN
= OV, V
CC
[1]
I
AL
Auto Latch Current
10
10
5
A
Note:
[1] All inputs driven to 0V, or V
cc
and outputs floating.
7
Z86C93
CPS DC-4020-12
DC ELECTRICAL CHARACTERISTICS
VCC = 5.0V
10%
T
A
= 0
C to +70
C
Typical
Sym
Parameter
Min
Max
at 25
C
Units
Conditions
Max Input Voltage
7
V
I
IN
250
A
V
CH
Clock Input High Voltage
3.8
V
CC
V
Driven by External Clock Generator
V
CL
Clock Input Low Voltage
0.03
0.8
V
Driven by External Clock Generator
V
IH
Input High Voltage (P0,P1,P2) 2.0
V
CC
V
V
IH
Input High Voltage (P3)
2.2
V
CC
V
V
IL
Input Low Voltage
0.3
0.8
V
V
OH
Output High Voltge
2.4
V
I
OH
= 2.0 mA
V
OH
Output High Voltage
V
CC
100mV
V
I
OH
= 100
A
V
OL
Output Low Voltage
0.4
V
I
OL
= +5 mA
V
RH
Reset Input High Voltage
3.8
V
CC
V
V
Rl
Reset Input Low Voltage
0.03
0.8
V
I
IL
Input Leakage
2
2
A
Test at 0V, V
CC
I
OL
Output Leakage
2
2
A
Test at 0V, V
CC
I
IR
Reset Input Current
180
A
V
RL
= 0V
I
CC
Supply Current
55
35
mA
@ 33 MHz [1]
40
25
mA
@ 25 MHz [1]
30
20
mA
@ 20 MHz [1]
I
CC1
Standby Current (HALT Mode)
20
15
mA
HALT Mode V
IN
= OV, V
CC
@ 33 MHz [1]
15
9
mA
HALT Mode V
IN
= OV, V
CC
@ 25 MHz [1]
12
7
mA
HALT Mode V
IN
= OV, V
CC
@ 20 MHz [1]
I
CC2
Standby Current
10
1
A
STOP Mode V
IN
= OV, V
CC
[1]
I
AL
Auto Latch Current
16
16
5
A
Note:
[1] All inputs driven to 0V, or V
cc
and outputs floating.
8
Z86C93
CPS DC-4020-12
AC CHARACTERISTICS
External Memory Read/Write Timing Diagram
R/W, /DM
9
12
3
16
20
4
5
8
11
6
17
15
7
14
2
Port 0
Port 1
/AS
/DS
(Read)
Port1
/DS
(Write)
A0 - A7
D0 - D7 IN
D0 - D7 OUT
A0 - A7
13
21
19
10
A0 - A7
A0-A7
1
A8 - A15
External Memory Read/Write Timing
9
Z86C93
CPS DC-4020-12
AC CHARACTERISTICS
External I/O or Memory Read and Write; DSR/DSW; WAIT Timing Table
T
A
= 0
C to +70
C
33 MHz
25 MHz
20 MHz
No
Sym
Parameter
Min
Max
Min
Max Min Max
Units
1
TdA(AS)
Address Valid To /AS Rise Delay
15
22
26
ns
2
ThAS(A)
/AS Rise To Address Hold Time
20
25
28
ns
3
TdAS(DI)
/AS Rise To Data In Req'd Valid Delay
96
130
160
ns
4
TwAS
/AS Low Width
15
28
36
ns
5
TdAZ(DSR)
Address Float To /DS Fall (Read)
0
0
0
ns
6
TwDSR
/DS (Read) Low Width
65
100
130
ns
7
TwDSW
/DS (Write) Low Width
40
65
75
ns
8
TdDSR(DI)
/DS Fall (Read) To Data in Req'd Valid Delay
55
85
100
ns
9
ThDSR(DI)
/DS Rise (Read) to Data In Hold Time
0
0
0
ns
10
TdDS(A)
/DS Rise To Address Active Delay
25
40
48
ns
11
TdDS(AS)
/DS Rise To /AS Delay
16
30
36
ns
12
TdR/W(AS)
R/W Valid To /AS Rise Delay
12
26
32
ns
13
TdDS(R/W)
/DS Rise To R/W Not Valid Delay
12
30
36
ns
14
TdDO(DSW)
Data Out To /DS Fall (Write) Delay
12
34
40
ns
15
ThDSW(DO)
/DS Rise (Write) To Data Out Hold Time
12
34
40
ns
16
TdA(DI)
Address Valid To Data In Req'd Valid Delay
115
160
200
ns
17
TdAS(DSR)
/AS Rise To /DS Fall (Read) Delay
30
40
48
ns
19
TdDM(AS)
/DM Valid To /AS Rise Delay
15
22
26
ns
20
TdDS(DM)
/DS Rise To /DM Valid Delay
15
34*
ns
21
ThDS(A)
/DS Rise To Address Valid Hold Time
35
ns
22
TdXT(SCR)
XTAL Falling to SCLK Rising**
35
ns
23
TdXT(SCF)
XTAL Falling to SCLK Falling**
45
ns
24
TdXT(DSRF)
XTAL Falling to/DS Read Falling**
35
ns
25
TdXT(DSRR)
XTAL Falling to /DS Read Rising**
35
ns
26
TdXT(DSWF)
XTAL Falling to /DS Write Falling**
45
ns
27
TdXT(DSWF)
XTAL Falling to /DS Write Rising**
35
ns
28
TsW(XT)
Wait Set-up Time
5
10*
ns
29
ThW(XT)
Wait Hold Time
15
15*
ns
30
TwW
Wait Width (One Wait Time)
20
25*
ns
Notes:
When using extended memory timing add 2 TpC.
Timing numbers given are for minimum TpC.
* Typical value to be characterized (25 MHz).
** External clock drive.
10
Z86C93
CPS DC-4020-12
XTAL/SCLK To DSR and DSW Timing
XTAL/SCLK To WAIT Timing
(25 MHz and 33 MHz Devices Only)
XTAL1
SCLK
DSR
27
26
25
24
23
22
DSW
XTAL1
SCLK
/AS
/DS
/WAIT
T1
T2
TW
TW
TW
T3
T1
31
32
30
(External Clock Drive)
/DS
(READ)
/DS
(Write)
11
Z86C93
CPS DC-4020-12
AC CHARACTERISTICS
Additional Timing Diagram
AC CHARACTERISTICS
Additional Timing Table
T
A
= 0
C to +70
C
33 MHz 25 MHz 20 MHz
No Symbol
Parameter
Min Max
Min
Max Min
Max Units Notes
1
TpC
Input Clock Period
30
1000
42
1000
50
1000
ns
[1]
2
TrC,TfC
Clock Imput Rise & Fall Times
5
10
10
ns
[1]
3
TwC
Input Clock Width
10
11
15
ns
[1]
4
TwTinL
Timer Input Low Width
75
75
75
ns
[2]
5
TwTinH
Timer Input High Width
3 TpC
3 TpC
3 TpC
[2]
6
TpTin
Timer Input Period
8 TpC
8 TpC
8 TpC
[2]
7
TrTin,TfTin
Timer Input Rise & Fall Times
100
100
100
ns
[2]
8A
TwIL
Interrupt Request Input Low Times
70
70
70
ns
[2,4]
8B
TwIL
Interrupt Request Input Low Times 5 TpC
5 TpC
5 TpC
[2,5]
9
TwIH
Interrupt Request Input High Times 3 TpC
3 TpC
3 TpC
[2,3]
Notes:
[1] Clock timing references use 3.8V for a logic 1 and 0.8V for a logic 0.
[2] Timing references use 2.0V for a logic 1 and 0.8V for a logic 0.
[3] Interrupt references request through Port 3.
[4] Interrupt request via Port 3 (P33-P31)`.
[5] Interrupt request via Port 30.
Additional Timing
Clock
1
3
4
8
2
2
3
T IN
IRQ N
6
5
7
7
9
12
Z86C93
CPS DC-4020-12
AC CHARACTERISTICS
Handshake Timing Diagrams
Input Handshake Timing
Data In
1
3
4
5
6
/DAV
(Input)
RDY
(Output)
Next Data In Valid
Delayed RDY
Delayed DAV
Data In Valid
2
Data Out
/DAV
(Output)
RDY
(Input)
Next Data Out Valid
Delayed RDY
Delayed DAV
Data Out Valid
7
8
9
10
11
Output Handshake Timing
13
Z86C93
CPS DC-4020-12
AC CHARACTERISTICS
Handshake Timing Table
T
A
= 0
C to +70
C
Data
No
Symbol
Parameter
Min
Max
Units
Direction
1
TsDI(DAV)
Data In Setup Time to /DAV
0
ns
In
2
ThDI(DAV)
RDY to Data In Hold Time
0
ns
In
3
TwDAV
/DAV Width
40
ns
In
4
TdDAVIf(RDYf)
/DAV to RDY Delay
70
ns
In
5
TdDAVIr(RDYr)
DAV Rise to RDY Wait Time
40
ns
In
6
TdRDYOr(DAVIf)
RDY Rise to DAV Delay
0
ns
In
7
TdD0(DAV)
Data Out to DAV Delay
TpC
ns
Out
8
TdDAV0f(RDYIf)
/DAV to RDY Delay
0
ns
Out
9
TdRDYIf(DAVOr)
RDY to /DAV Rise Delay
70
ns
Out
10
TwRDY
RDY Width
40
ns
Out
11
TdRDYIr(DAVOf)
RDY Rise to DAV Wait Time
40
ns
Out
1994 by Zilog, Inc. All rights reserved. No part of this document
may be copied or reproduced in any form or by any means
without the prior written consent of Zilog, Inc. The information in
this document is subject to change without notice. Devices sold
by Zilog, Inc. are covered by warranty and patent indemnification
provisions appearing in Zilog, Inc. Terms and Conditions of Sale
only. Zilog, Inc. makes no warranty, express, statutory, implied or
by description, regarding the information set forth herein or
regarding the freedom of the described devices from intellectual
property infringement. Zilog, Inc. makes no warranty of mer-
chantability or fitness for any purpose. Zilog, Inc. shall not be
responsible for any errors that may appear in this document.
Zilog, Inc. makes no commitment to update or keep current the
information contained in this document.
Zilog's products are not authorized for use as critical compo-
nents in life support devices or systems unless a specific written
agreement pertaining to such intended use is executed between
the customer and Zilog prior to use. Life support devices or
systems are those which are intended for surgical implantation
into the body, or which sustains life whose failure to perform,
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result in
significant injury to the user.
Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
Telex 910-338-7621
FAX 408 370-8056