Z86E61/E63 Z8

MCU

WITH

16K/32K EPROM

P R E L I M I N A R Y

RELIMINAR

RODUCT

PECIFICA

TION

FEATURES

8-Bit CMOS Microcontroller

40-Pin DIP, 44-Pin PLCC Style Packages

4.5V to 5.5V Operating Range

Clock Speeds: 16 and 20 MHz

Low Power Consumption: 275 mW (max)

Fast Instruction Pointer: 1.0 ms @ 12 MHz

Two Standby Modes: STOP and HALT

32 Input/Output Lines

Full-Duplex UART

All Digital Inputs are TTL Levels

Auto Latches

Z86E61/E63

CMOS Z8

16K/32K EPROM

ICROCONTROLLER

High Voltage Protection on High Voltage Inputs

RAM and EPROM Protect

EPROM: 16 Kbytes Z86E61

32 Kbytes Z86E63

256 Bytes Register File
- 236 Bytes of General-Purpose RAM
- 16 Bytes of Control and Status Registers
- 4 Bytes for Ports

Two Programmable 8-Bit Counter/Timers Each
with 6-Bit Programmable Prescaler

Six Vectored, Priority Interrupts from Eight
Different Sources

On-Chip Oscillator that Accepts a Crystal, Ceramic
Resonator, LC, or External Clock Drive

GENERAL DESCRIPTION

The Z86E61/E63 microcontrollers are members of the Z8

single-chip microcontroller family with 16K/32 Kbytes of
EPROM and 236 bytes of general-purpose RAM. Offered
in 40-pin DIP or 44-pin PLCC package styles, these de-
vices are pin-compatible EPROM versions of the Z86C61/
63. The ROMless pin option is available on the 44-pin
versions only.

With 4 Kbytes of ROM and 236 bytes of general-purpose
RAM, the Z86E61/E63 offers fast execution, efficient use of
memory, sophisticated interrupts, input/output bit manipu-
lation capabilities, and easy hardware/software system
expansion.

For applications demanding powerful I/O capabilities, the
Z86E61/E63 offers 32 pins dedicated to input and output.
These lines are grouped into four ports. Each port consists
of eight lines, and is configurable under software control to
provide timing, status signals, serial or parallel
I/O with or without handshake, and an address/data bus
for interfacing external memory.

The Z86E61/E63 can address both external memory and
preprogrammed ROM, making it well suited for high-
volume applications or where code flexibility is required.

Z86E61/E63 Z8

MCU

WITH

16K/32K EPROM

P R E L I M I N A R Y

GENERAL DESCRIPTION

(Continued)

There are three basic address spaces available to support
this configuration: Program Memory, Data Memory, and
236 general-purpose registers.

To unburden the system from coping with real-time tasks
such as counting/timing and serial data communication,
the Z86E61/E63 offers two on-chip counter/timers with a
large number of user selectable modes (Figure 1).

Notes:

All Signals with a preceding front slash, "/", are active Low, e.g.,
B//W (WORD is active Low); /B/W (BYTE is active Low, only).

Power connections follow conventional descriptions below:

Connection

Circuit

Device

Power

Ground

GND

Port 3

UART

Counter/

Timers

(2)

Interrupt

Control

Port 2

I/O

(Bit Programmable)

ALU

FLAGS

Pointer

256 x 8-Bit

Machine Timing and

Instruction Control

Prg. Memory

16K/32K

Program

Counter

Vcc

GND

XTAL

Port 0

Output

Input

Address or I/O

(Nibble Programmable)

Port 1

Address/Data or I/O

(Byte Programmable)

/AS /DS R//W /RESET

Figure 1. Z86E61/E63 Functional Block Diagram

Z86E61/E63 Z8

MCU

WITH

16K/32K EPROM

P R E L I M I N A R Y

PIN DESCRIPTION

Standard Mode

Table 1. 40-Pin DIP Pin Identification

Standard Mode
Pin #

Symbol

Function

Direction

Power Supply

Input

XTAL2

Crystal, Oscillator Clock

Output

XTAL1

Crystal, Oscillator Clock

Input

P37

Port 3, Pin 7

Output

P30

Port 3, Pin 0

Input

/RESET

Reset

Input

R//W

Read/Write

Output

/DS

Data Strobe

Output

/AS

Address Strobe

Output

P35

Port 3, Pin 5

Output

GND

Ground

Input

P32

Port 3, Pin 2

Input

13-20

P07-P00

Port 0, Pins 0,1,2,3,4,5,6,7 In/Output

21-28

P17-P10

Port 1, Pins 0,1,2,3,4,5,6,7 In/Output

P34

Port 3, Pin 4

Output

P33

Port 3, Pin 3

Input

31-38

P27-P20

Port 2, Pins 0,1,2,3,4,5,6,7 In/Output

P31

Port 3, Pin 1

Input

P36

Port 3, Pin 6

Output

P36

P31

P21

P27

P26

P25

P24

P23

P22

VCC

XTAL2

P37

P30

/RESET

R//W

/DS

XTAL1

GND

P32

P00

P01

P20

P33

P34

P17

P16

Z86E61

/E63

DIP

/AS

P35

P02

P03

P06

P07

P05

P04

P13

P15

P14

P12

P11

P10

Figure 2. 40-Pin DIP Pin Configuration

Z86E61/E63 Z8

MCU

WITH

16K/32K EPROM

P R E L I M I N A R Y

PIN DESCRIPTION

(Continued)

Standard Mode

Figure 3. 44-Pin PLCC Pin Configuration

N/C

P30

P37

AL1

AL2

VCC

P36

P31

P27

P26

P25

P03

P04

P05

P06

P07

P10

P12

P13

P14

N/C

P24

P23

P22

P21

P20

P33

P34

P17

P16

P15

/RESET

R//W

/DS

/AS

P35

GND

P32

P00

P01

P02

R//RL

Z86E61/E63

PLCC

44 43 42 41 40

18 19 20 21 22 23 24 25 26 27 28

Standard Mode
Pin #

Symbol

Function

Direction

Power Supply

Input

XTAL2

Crystal, Osc. Clock

Output

XTAL1

Crystal, Osc. Clock

Input

P37

Port 3, Pin 7

Output

P30

Port 3, Pin 0

Input

N/C

Not Connected

Input

/RESET

Reset

Input

R//W

Read/Write

Output

/DS

Data Strobe

Output

/AS

Address Strobe

Output

P35

Port 3, Pin 5

Output

GND

Ground

Input

P32

Port 3, Pin 2

Input

Standard Mode
Pin #

Symbol

Function

Direction

14-16

P02-P00

Port 0, Pins 0,1,2

In/Output

R//RL

ROM/ROMless control

Input

18-22

P07-P03

Port 0, Pins 3,4,5,6,7

In/Output

23-27

P10-P14

Port 1, Pins 0,1,2,3,4

In/Output

N/C

Not Connected

Input

29-31

P17-P15

Port 1, Pins 5,6,7

In/Output

P34

Port 3, Pin 4

Output

P33

Port 3, Pin 3

Input

34-38

P24-P20

Port 2, Pins 0,1,2,3,4

In/Output

N/C

Not Connected

Input

40-42

P27-P25

Port 2, Pins 5,6,7

In/Output

P31

Port 3, Pin 1

Input

P36

Port 3, Pin 6

Output

Table 2. 44-Pin PLCC Pin Identification

Z86E61/E63 Z8

MCU

WITH

16K/32K EPROM

P R E L I M I N A R Y

PIN DESCRIPTION

EPROM Mode

N/C

/OE

/PGM

A14

A13

A12

A11

A10

VCC

XTAL2

N/C

/CE

/RESET

N/C

XTAL1

GND

EPM

VPP

N/C

Z86E61

/E63

DIP

N/C

Figure 4. 40-Pin DIP Pin Configuration

Table 3. 40-Pin DIP Pin Identification

EPROM Mode
Pin #

Symbol

Function

Direction

Power Supply

Input

XTAL2

Crystal, Osc. Clock

Output

XTAL1

Crystal, Osc. Clock

Input

N/C

Not Connected

Input

/CE

Chip Enable

Input

/RESET

Reset

Input

7-10

N/C

Not Connected

Input

GND

Ground

Input

EPM

EPROM Prog Mode

Input

13-20

A7-A0

Address 0,1,2,3,4,5,6,7

Input

21-28

D7-D0

Data 0,1,2,3,4,5,6,7

In/Output

N/C

Not Connected

Input

Prog Voltage

Input

31-37

A14-A8

Address 8,9,10,11,12,13,14

Input

/PGM

Prog Mode

Input

/OE

Output Enable

Input

N/C

Not Connected

Input

Z86E61/E63 Z8

MCU

WITH

16K/32K EPROM

P R E L I M I N A R Y

N/C

/CE

N/C

AL1

AL2

VCC

N/C

/OE

/PGM

A14

A13

N/C

A12

A11

A10

VPP

N/C

/RESET

N/C

GND

EPM

N/C

Z86E61/E63

PLCC

44 43 42 41 40

18 19 20 21 22 23 24 25 26 27 28

PIN DESCRIPTION

(Continued)

EPROM Mode

EPROM Mode
Pin #

Symbol

Function

Direction

Power Supply

Input

XTAL2

Crystal, Osc. Clock

Input

XTAL1

Crystal, Osc. Clock

Input

N/C

Not Connected

Input

/CE

Chip Enable

Input

N/C

Not Connected

Input

/RESET

Reset

Input

8-11

N/C

Not Connected

Input

GND

Ground

Input

EPM

EPROM Prog Mode

Input

14-16

A0-A2

Address 0,1,2

Input

N/C

Not Connected

Input

EPROM Mode
Pin #

Symbol

Function

Direction

18-22

A7-A3

Address 3,4,5,6,7

Input

23-27

D4-D0

Data 0,1,2,3,4

In/Output

N/C

Not Connected

Input

29-31

D7-D5

Data 5,6,7

In/Output

N/C

Not Connected

Input

Prog Voltage

Input

34-38

A12-A8

Address 8,9,10,11,12

Input

N/C

Not Connected

Input

40-41

A13-A14

Address 13, 14

Input

/PGM

Prog Mode

Input

/OE

Output Enable

Input

N/C

Not Connected

Input

Table 4. 44-Pin PLCC Pin Identification

Figure 5. 44-Pin PLCC Pin Configuration

Z86E61/E63 Z8

MCU

WITH

16K/32K EPROM

P R E L I M I N A R Y

PIN FUNCTIONS

ROMless

(input, active Low). Connecting this pin to GND

disables the internal ROM and forces the device to func-
tion as a Z86C91 ROMless Z8 (see the Z86C91 product
specification for more information). When left unconnected
or pulled High to V

, the device functions as a normal

Z86E61/E63 EPROM version.

Note:

This pin is only avail-

able on the 44-pin versions of the Z86E61/E63.

/DS

(output, active Low). Data Strobe is activated once for

each external memory transfer. For a READ operation,
data must be available prior to the trailing edge of /DS. For
WRITE operations, the falling edge of /DS indicates that
output data is valid.

/AS

(output, active Low). Address Strobe is pulsed once at

the beginning of each machine cycle. Address output is
through Port 1 for all external programs. Memory address
transfers are valid at the trailing edge of /AS. Under
program control, /AS can be placed in the high-
impedance state along with Ports 0 and 1, Data Strobe,
and Read/Write.

XTAL2, XTAL1

Crystal 2, Crystal 1 (time-based input and

output, respectively). These pins connect a parallel-
resonant crystal, ceramic resonator, LC, or any external
single-phase clock to the on-chip oscillator and buffer.

R//W

(output, write Low). The Read/Write signal is Low

when the MCU is writing to the external program or data
memory.

/RESET

(input, active Low). To avoid asynchronous and

noisy reset problems, the Z86E61/E63 is equipped with a
reset filter of four external clocks (4TpC). If the external
/RESET signal is less than 4TpC in duration, no reset
occurs.

On the fifth clock after the /RESET is detected, an internal
RST signal is latched and held for an internal register count
of 18 external clocks, or for the duration of the external
/RESET, whichever is longer. During the reset cycle, /DS is
held active Low while /AS cycles at a rate of TpC/2. When
/RESET is deactivated, program execution begins at loca-
tion 000C (HEX). Power-up reset time must be held low for
50 ms, or until V

is stable, whichever is longer.

Port 0

(P07-P00

Port 0 is an 8-bit, nibble programmable,

bidirectional, TTL compatible port. These eight I/O lines

can be configured under software control as a nibble I/O
port, or as an address port for interfacing external memory.
When used as an I/O port, Port 0 may be placed under
handshake control. In this configuration, Port 3, lines P32
and P35 are used as the handshake control /DAV0 and
RDY0 (Data Available and Ready). Handshake signal
assignment is dictated by the I/O direction of the upper
nibble P07-P04. The lower nibble must have the same
direction as the upper nibble to be under handshake
control.

For external memory references, Port 0 can provide ad-
dress bits A11-A8 (lower nibble) or A15-A8 (lower and
upper nibbles) depending on the required address space.
If the address range requires 12 bits or less, the upper
nibble of Port 0 can be programmed independently as I/O
while the lower nibble is used for addressing. If one or both
nibbles are needed for I/O operation, they must be config-
ured by writing to the Port 0 Mode register.

In ROMless mode, after a hardware reset, Port 0 lines are
defined as address lines A15-A8, and extended timing is
set to accommodate slow memory access. The initializa-
tion routine can include reconfiguration to eliminate this
extended timing mode (Figure 8).

Port 1

(P17-P10)

Port 1 is an 8-bit, byte programmable,

bidirectional, TTL compatible port. It has multiplexed Ad-
dress (A7-A0) and Data (D7-D0) ports. For Z86E61/E63,
these eight I/O lines can be programmed as input or output
lines or are configured under software control as an
address/data port for interfacing external memory. When
used as an I/O port, Port 1 can be placed under handshake
control. In this configuration, Port 3 lines, P33 and P34, are
used as the handshake controls RDY1 and /DAV1.

Memory locations greater than 16384 (E61) or 32768 (E63)
are referenced through Port 1. To interface external memory,
Port 1 must be programmed for the multiplexed Address/
Data mode. If more than 256 external locations are re-
quired, Port 0 must output the additional lines.

Port 1 can be placed in high-impedance state along with
Port 0, /AS, /DS, and R//W, allowing the MCU to share
common resources in multiprocessor and DMA applica-
tions. Data transfers are controlled by assigning P33 as a
Bus Acknowledge input, and P34 as a Bus Request output
(Figure 9).

Z86E61/E63 Z8

MCU

WITH

16K/32K EPROM

P R E L I M I N A R Y

Port 3

(P37-P30)

Port 3 is an 8-bit, CMOS compatible four-

fixed input and four-fixed output port. These eight I/O lines
have four-fixed (P33-P30) input and four-fixed (P37-P34)

output ports. Port 3, when used as serial I/O, is pro-
grammed as serial in and serial out, respectively
(Figure 9).

Z86E61

/E63

MCU

Port 3
(I/O or Control)

Figure 9. Port 3 Configuration

Port 3 is configured under software control to provide the
following control functions: handshake for Ports 0 and 2
(/DAV and RDY); four external interrupt request signals

(IRQ3-IRQ0); timer input and output signals (T

and T

OUT

Data Memory Select (/DM) and EPROM control signals
(P30 = /CE, P31 = /OE, P32 = EPM and P33 = V

Table 5. Port 3 Pin Assignments

Pin

I/O

CTC1

Int.

P0 HS

P1 HS

P2 HS

UART

Ext

EPROM

P30

IRQ3

Serial In

/CE

P31

IRQ2

D/R

/OE

P32

IRQ0

D/R

EPM

P33

IRQ1

D/R

P34

OUT

R/D

P35

OUT

R/D

P36

OUT

R/D

P37

OUT

Serial Out

IRQ4

IRQ5

Notes:

HS = Handshake Signals
D = Data Available
R = Ready

Z86E61/E63 Z8

MCU

WITH

16K/32K EPROM

P R E L I M I N A R Y

UART OPERATION

Port 3 lines, P37 and P30, are programmed as serial I/O
lines for full-duplex serial asynchronous receiver/trans-
mitter operation. The bit rate is controlled by Counter/
Timer0.

The Z86E61/E63 automatically adds a start bit and two
stop bits to transmitted data (Figure 10). Odd parity is also
available as an option. Eight data bits are always transmit-

ted, regardless of parity selection. If parity is enabled, the
eighth bit is the odd parity bit. An interrupt request (IRQ4)
is generated on all transmitted characters.

Received data must have a start bit, eight data bits, and at
least one stop bit. If parity is on, bit 7 of the received data
is replaced by a parity error flag. Received characters
generate the IRQ3 interrupt request.

Start Bit

Eight Data Bits

Transmitted Data (No Parity)

Two Stop Bits

SP SP

Start Bit

Seven Data Bits

Transmitted Data (With Parity)

Odd Parity

Two Stop Bits

SP SP

Start Bit

Eight Data Bits

Received Data (No Parity)

One Stop Bit

Start Bit

Seven Data Bits

Received Data (With Parity)

Parity Error Flag

One Stop Bit

Figure 10. Serial Data Formats

Auto Latch.

The Auto Latch puts valid CMOS levels on all

CMOS inputs that are not externally driven. This reduces
excessive supply current flow in the input buffer when it is
not driven by any source.

Note:

P33-P30 inputs differ from the Z86C61/C63 in that

there is no clamping diode to V

because of the EPROM

high voltage detection circuits. Exceeding the V

maxi-

mum specification during standard operating mode may
cause the device to enter EPROM mode

ADDRESS SPACE

Program Memory. The Z86E61/E63 can address 48
Kbytes (E61) or 32 Kbytes (E63) of external program
memory (Figure 11). The first 12 bytes of program memory
are reserved for the interrupt vectors. These locations
contain six 16-bit vectors that correspond to the six
available interrupts. For EPROM mode, byte 13 to byte

16383 (E61) or 32767 (E63) consists of on-chip EPROM. At
addresses 16384 (E61) or 32768 (E63) and above, the
Z86E61/E63 executes external program memory fetches.
In ROMless mode, the Z86E61/E63 can address up to 64
Kbytes of program memory. Program execution begins at
external location 000C (HEX) after a reset.

Z86E61/E63 Z8

MCU

WITH

16K/32K EPROM

P R E L I M I N A R Y

access registers directly or indirectly through an 8-bit
address field. The Z86E61/E63 also allows short 4-bit
register addressing using the Register Pointer (Figure 14).
In the 4-bit mode, the Register File is divided into 16
working register groups, each occupying 16 continuous
locations. The Register Pointer addresses the starting
location of the active working register group.

Stack.

The Z86E61/E63 has a 16-bit Stack Pointer (R255-

R254) used for external stacks that reside anywhere in the
data memory for the ROMless mode, but only from 16384
(E61) or 32768 (E63) to 65535 in the EPROM mode. An
8-bit Stack Pointer (R255) is used for the internal stack that
resides within the 236 general-purpose registers (R239-
R4). The high byte of the Stack Pointer (SPH Bits 15-8) can
be use as a general purpose register when using internal
stack only.

External

ROM and RAM

Location of

First Byte of

Instruction

Executed

After RESET

Interrupt

Vector

(Lower Byte)

Interrupt

Vector

(Upper Byte)

IRQ5

IRQ4

IRQ3

IRQ2

IRQ1

IRQ0

IRQ5

65535

On-Chip PROM

16384 (E61)
32768 (E63)

16383 (E61)
32767 (E63)

Figure 11. Program Memory Configuration

Data Memory

(/DM)

The EPROM version can address up

to 48 Kbytes (E61) or 32 Kbytes (E63) of external data
memory space beginning at location 16384 (E61) or 32768
(E63). The ROMless version can address up to 64 Kbytes
of external data memory. External data memory may be
included with, or separated from, the external program
memory space. /DM, an optional I/O function that can be
programmed to appear on pin P34, is used to distinguish
between data and program memory space (Figure 12).
The state of the /DM signal is controlled by the type
instruction being executed. An LDC opcode references
PROGRAM (/DM inactive) memory, and an LDE instruction
references DATA (/DM active Low) memory.

Register File.

The register file consists of four I/O port

registers, 236 general-purpose registers, and 16 control
and status registers (Figure 13). The instructions can

65535

16383 (E61)
32767 (E63)

External

Data

Memory

Not Addressable

32768 (E63)
16384 (E61)

Figure 12. Data Memory Configuration

Z86E61/E63 Z8

MCU

WITH

16K/32K EPROM

P R E L I M I N A R Y

ADDRESS SPACE

(Continued)

Stack Pointer (Bits 7-0)

R255

Stack Pointer (Bits 15-8)

Program Control Flags

Interrupt Mask Register

Interrupt Request Register

Interrupt Priority Register

Ports 0-1 Mode

Port 3 Mode

Port 2 Mode

T0 Prescaler

Timer/Counter0

T1 Prescaler

Timer/Counter1

Timer Mode

Serial I/O

General-Purpose

Registers

Port 3

Port 2

Port 1

Port 0

R254

R253

R252

R251

R250

R249

R248

R247

R246

R245

R244

R243

R242

R241

R240

R239

SPL

SPH

FLAGS

IMR

IRQ

IPR

P01M

P3M

P2M

PRE0

PRE1

TMR

SIO

LOCATION

IDENTIFIERS

The upper nibble of the register file address
provided by the register pointer specifies
the active working-register group.

R253
(Register Pointer)

I/O Ports

Specified Working

The lower nibble
of the register
file address
provided by the
instruction points
to the specified
register.

R15 to R0

R15 to R4

R3 to R0

R15 to R0

·
·
·
·
·

·
·
·
·
·
·

Figure 14. Register Pointer

Figure 13. Register File

Z86E61/E63 Z8

MCU

WITH

16K/32K EPROM

P R E L I M I N A R Y

FUNCTIONAL DESCRIPTION

Counter/Timers.

There are two 8-bit programmable

counter/timers (T0-T1), each driven by its own 6-bit pro-
grammable prescaler. The T1 prescaler is driven by inter-
nal or external clock sources; however, the T0 prescaler is
driven by the internal clock only (Figure 15).

The 6-bit prescalers can divide the input frequency of the
clock source by any integer number from 1 to 64. Each
prescaler drives its counter, which decrements the value
(1 to 256) that has been loaded into the counter. When both
the counters and prescalers reach the end of the count,
a timer interrupt request, IRQ4 (T0) or IRQ5 (T1), is
generated.

The counter is programmed to start, stop, restart to con-
tinue, or restart from the initial value. The counters can also

be programmed to stop upon reaching zero (single pass
mode) or to automatically reload the initial value and
continue counting (modulo-n continuous mode).

The counter, but not the prescalers, are read at any time
without disturbing their value or count mode. The clock
source for T1 is user-definable and is either the internal
microprocessor clock divided-by-four, or an external sig-
nal input through Port 3. The Timer Mode register config-
ures the external timer input (P31) as an external clock, a
trigger input that can be retriggerable or non-retriggerable,
or as a gate input for the internal clock. Port 3 line P36 also
serves as a timer output (T

OUT

) through which T0, T1, or the

internal clock can be output. The counter/timers are cas-
caded by connecting the T0 output to the input of T1.

Figure 15. Counter/Timers Block Diagram

OSC

PRE0

Initial Value

Current Value

6-Bit

Down

Counter

8-bit

Down

Counter

6-Bit

Down

Counter

8-Bit

Down

Counter

PRE1

Initial Value

Current Value

Clock
Logic

IRQ4

IRQ5

Internal Data Bus

Write

Read

Internal Clock
Gated Clock
Triggered Clock

Tin P31

Write

Read

Internal Data Bus

External Clock

Internal
Clock

Serial I/O
Clock

TOUT
P36

Z86E61/E63 Z8

MCU

WITH

16K/32K EPROM

P R E L I M I N A R Y

FUNCTIONAL DESCRIPTION

(Continued)

Interrupts.

The Z86E61/E63 has six different interrupts

from eight different sources. The interrupts are maskable
and prioritized. The eight sources are divided as follows:
four sources are claimed by Port 3 lines P33-P30, one in
Serial Out, one in Serial In, and two in the counter/timers
(Figure 16). The Interrupt Mask Register globally or indi-
vidually enables or disables the six interrupt requests.
When more than one interrupt is pending, priorities are
resolved by a programmable priority encoder that is con-
trolled by the Interrupt Priority register (refer to Table 5).

All Z86E61/E63 interrupts are vectored through locations
in the program memory. When an interrupt machine cycle
is activated, an interrupt request is granted. Thus, this
disables all of the subsequent interrupts, saves the Pro-
gram Counter and Status Flags, and then branches to the
program memory vector location reserved for that inter-
rupt. This memory location and the next byte contain the
16-bit address of the interrupt service routine for that
particular interrupt request.

To accommodate polled interrupt systems, interrupt in-
puts are masked and the Interrupt Request register is
polled to determine which of the interrupt requests need
service. Software initialized interrupts are supported by
setting the appropriate bit in the Interrupt Request Reg-
ister (IRQ).

Internal interrupt requests are sampled on the falling edge
of the last cycle of every instruction, and the interrupt
request must be valid 5TpC before the falling edge of the
last clock cycle of the currently executing instruction.

For the ROMless mode, when the device samples a valid
interrupt request, the next 48 (external) clock cycles are
used to prioritize the interrupt, and push the two PC bytes
and the FLAG register on the stack. The following nine
cycles are used to fetch the interrupt vector from external
memory. The first byte of the interrupt service routine is
fetched beginning on the 58th TpC cycle following the
internal sample point, which corresponds to the 63rd TpC
cycle following the external interrupt sample point.

IRQ

IMR

IPR

PRIORITY

LOGIC

Global

Interrupt

Enable

Vector Select

Interrupt
Request

IRQ0 - IRQ5

Figure 16. Interrupt Block Diagram

Z86E61/E63 Z8

MCU

WITH

16K/32K EPROM

P R E L I M I N A R Y

Clock. The Z86E61/E63 on-chip oscillator has a high
gain, parallel resonant amplifier for connection to a crystal,
LC, ceramic resonator, or any suitable external clock
source (XTAL1 = Input, XTAL2 = Output). The crystal
should be AT cut, 1 MHz to 16 MHz max; series resistance

(RS) is less than or equal to 100 Ohms. The crystal should
be connected across XTAL1 and XTAL2 using the recom-
mended capacitors (10 pF < CL < 100 pF) from each pin
to ground (Figure 17).

Note:

Actual capacitor value speci-

fied by crystal manufacturer.

XTAL1

XTAL2

XTAL1

XTAL2

XTAL1

XTAL2

Ceramic Resonator
or Crystal

LC Clock

External Clock

Pin 11

Figure 17. Oscillator Configuration

Z86E61/E63 User Modes

The Z86E61/E63 uses separate AC timing cycles for the
different User Modes available. Table 6 shows the Z86E61/
E63 User Modes. Table 7 shows the timing of the program-
ming waveforms.

User MODE 1 EPROM Read

The Z86E61/E63 EPROM read cycle is provided so that the
user may read the Z86E61/E63 as a standard 27128 (E61)
or 27256 (E63) EPROM. This is accomplished by driving
the /EPM pin (P32) to V

and activating /CE and /OE. /PGM

remains inactive. This mode is not valid after execution of
an EPROM protect cycle. Timing for the EPROM read cycle
is shown in Figure 18.

PROGRAMMING

HALT.

Turns off the internal CPU clock but not the XTAL

oscillation. The counter/timers and external interrupts IRQ0,
IRQ1, IRQ2, and IRQ3 remain active. The devices are
recovered by interrupts, either externally or internally gen-
erated. An interrupt request must be executed (enabled)
to exit HALT mode. After the interrupt service routine, the
program continues from the instruction after the HALT.

STOP.

This instruction turns off the internal clock and

external crystal oscillation, and reduces the standby cur-
rent to 5

A (typical) or less. The STOP mode is terminated

by a reset, which causes the processor to restart the
application program at address 000C (HEX).

In order to enter STOP (or HALT) mode, it is necessary to
first flush the instruction pipeline to avoid suspending
execution in mid-instruction. To do this, the user must
execute a NOP (opcode = OFFH) immediately before the
appropriate SLEEP instruction. i.e.,

FF NOP

; clear the pipeline

6F STOP

; enter STOP mode

FF NOP

; clear the pipeline

7F HALT

; enter HALT mode

User MODE 2 EPROM Program

The Z86E61/E63 Program function conforms to the Intelli-
gent programming algorithm. The device is programmed
with V

at 6.0V and V

= 12.5V. Programming pulses are

applied in 1 ms increments to a maximum of 25 pulses
before proper verification. After verification, a program-
ming pulse of three times the duration of the cycles
necessary to program the device is issued to ensure
proper programming. After all addresses are programmed,
a final data comparison is executed and the programming
cycle is complete. Timing for the Z86E61/E63 program-
ming cycle is shown in Figure 18.

Z86E61/E63 Z8

MCU

WITH

16K/32K EPROM

P R E L I M I N A R Y

PROGRAMMING

(Continued)

User Mode 3: PROM Verify

The Program Verify cycle is used as part of the intelligent
programming algorithm to insure data integrity under
worst-case conditions. It differs from the EPROM Read
cycle in that V

is active and V

must be driven to 6.0V.

Timing is shown in Figure 18.

User Modes 4 and 5: EPROM and RAM Protect

To extend program security, EPROM and RAM protect
cycles are provided for the Z86E61/E63. Execution of the

EPROM protect cycle prohibits proper execution of the
EPROM Read, EPROM Verify, and EPROM programming
cycles. Execution of the RAM protect cycle disables ac-
cesses to the upper 128 bytes of register memory (exclud-
ing mode and configuration registers), but first the user's
program must set bit 6 of the IMR (R251). Timing is shown
in Figures 20 and 21.

User Modes.

Table 6 shows the programming voltage of

each mode of the Z86E61/E63.

Table 6. OTP Programming Table

User/Test Mode

Device Pins

Port 1

Device Pin No.

P33

P32

P30

P31

P20

CNFG

User Modes

EPM

/CE

/OE

/PGM

ADDR

Data

EPROM Read

Addr

5.0V

Out

Program

Addr

6.0V

Program Verify

Addr

6.0V

Out

EPROM Protect

6.0V

RAM Protect

6.0V

Notes:

= 12.0V

0.5V

= 12.0V

0.5V

= 5V

= 0V

XX = Irrelevant
I

during programming = 40 mA maximum.

during programming, verify, or read = 40 mA maximum.

Z86E63 Signal Description for EPROM
Program/Read

The following signals are required to correctly program or
read the Z86E63 device.

ADDR.

The address must remain stable throughout the

program read cycle.

DATA.

The I/O data bus must be stable during program-

ming (/OE High, /PGM Low, V

High). During read the data

bus outputs data.

XCLK.

A clock is required to clock the /RESET signal into

the registers before programming.

A constant clock can be applied, or the XCLK input can be
toggled a minimum of 12 cycles before any programming
or verify function begins. The maximum clock frequency to
be applied when in the EPROM mode is 12 MHz.

/RESET.

The reset input can be held to a constant Low or

High value throughout normal programming. It must be
held High to program the EPROM protect option bit. Also,
any time the /RESET input changes state the XCLK must be
clocked a minimum of 12 times to clock the /RESET
through the reset filter.

/OE.

When the device is placed in EPROM mode, the /OE

input also serves as the precharge for the sense amp. The
precharge signal should be Low for the first half of the
stable address and High for the second half. The PRECHG
signal is inverted from the /OE signal so the /OE should be
High on the first half and Low on the second half, or stable
address. The EPROM output data should be sampled
during the second half of stable address.

The access time of the EPROM is defined in later sections.
This two part calculation of access time is required be-
cause this is a precharged sense amp with a precharge
clock.

Z86E61/E63 Z8

MCU

WITH

16K/32K EPROM

P R E L I M I N A R Y

Table 7. Timing of Programming Waveforms

Parameters

Name

Min

Max

Units

Address Setup Time

Data Setup Time

Setup

Setup Time

Chip Enable Setup Time

Program Pulse Width

0.95

Data Hold Time

/OE Setup Time

Data Access Time

200

Data Output Float Time

100

Overprogram Pulse Width

2.85

EPM Setup Time

/PGM Setup Time

Address to /OE Setup Time

Option Program Pulse Width

Figure 18. EPROM Read

Data

VIH

VIL

Invalid

Valid

Invalid

Valid

VIH

VIL

Address Stable

Address

Address Stable

0 Min

EPM

VIL

VCC

4.5V

/CE

VIH

VIL

/OE

VIH

VIL

VPP

VIL

5.5V

/PGM

VIH

VIL

Z86E61/E63 Z8

MCU

WITH

16K/32K EPROM

P R E L I M I N A R Y

ABSOLUTE MAXIMUM RATINGS

Symbol

Description

Min

Max

Units

Supply Voltage*

0.3

+ 7.0

STG

Storage Temp

+150

Oper Ambient Temp

Stresses greater than those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the de-
vice. This is a stress rating only; operation of the device at
any condition above those indicated in the operational
sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for an extended pe-
riod may affect device reliability.

Notes:

* Voltages on all pins with respect to GND.
See Ordering Information

STANDARD TEST CONDITIONS

The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to GND.
Positive current flows into the referenced pin (Figure 23).

From Output

Under Test

150 pF

Figure 23. Test Load Diagram

Z86E61/E63 Z8

MCU

WITH

16K/32K EPROM

P R E L I M I N A R Y

DC CHARACTERISTICS

= 0

C to +70

Typical

Sym

Parameter

Min

Max

@ 25

Units

Conditions

Max Input Voltage

250

Max Input Voltage

P33-P30 Only

Clock Input High Voltage

3.8

+ 0.3

Driven by External Clock Generator

Clock Input Low Voltage

0.3

0.8

Driven by External Clock Generator

Input High Voltage

2.0

+ 0.3

Input Low Voltage

0.3

0.8

Output High Voltage

2.4

= 2.0 mA

Output Low Voltage

0.4

= +2.0 mA

Reset Input High Voltage

3.8

+ 0.3

Reset Input Low Voltage

0.3

0.8

Input Leakage

0V V

+ 5.25V

Output Leakage

0V V

+ 5.25V

Reset Input Current

= + 5.25V, V

= 0V

Supply Current

@ 16 MHz

@ 20 MHz

CC1

Standby Current

HALT Mode V

= 0V, V

@ 16 MHz

HALT Mode V

= 0V, V

@ 20 MHz

CC2

Standby Current

STOP Mode V

= 0V, V

@ 16 MHz

STOP Mode V

= 0V, V

@ 20 MHz

Notes:

CC2

requires loading TMR (%F1H) with any value prior to STOP execution.

Use this sequence:

LD TMR,#00
NOP
STOP

Z86E61/E63 Z8

MCU

WITH

16K/32K EPROM

P R E L I M I N A R Y

AC CHARACTERISTICS

External I/O or Memory Read and Write Timing Table

= 0

C to +70

16 MHz

20 MHz

Symbol

Parameter

Min

Max

Min

Max

Units

Notes

TdA(AS)

Address Valid to /AS Rise Delay

[2,3]

TdAS(A)

/AS Rise to Address Float Delay

[2,3]

TdAS(DR)

/AS Rise to Read Data Req'd Valid

180

160

[1,2,3]

TwAS

/AS Low Width

[2,3]

TdAZ(DS)

Address Float to /DS Fall

TwDSR

/DS (Read) Low Width

135

130

[1,2,3]

TwDSW

/DS (Write) Low Width

[1,2,3]

TdDSR(DR)

/DS Fall to Read Data Req'd Valid

100

[1,2,3]

ThDR(DS)

Read Data to /DS Rise Hold Time

[2,3]

TdDS(A)

/DS Rise to Address Active Delay

[2,3]

TdDS(AS)

/DS Rise to /AS Fall Delay

[2,3]

TdR/W(AS)

R//W Valid to /AS Rise Delay

[2,3]

TdDS(R/W)

/DS Rise to R//W Not Valid

[2,3]

TdDW(DSW)

Write Data Valid to /DS Fall (Write) Delay

[2,3]

TdDS(DW)

/DS Rise to Write Data Not Valid Delay

[2,3]

TdA(DR)

Address Valid to Read Data Req'd Valid

200

[1,2,3]

TdAS(DS)

/AS Rise to /DS Fall Delay

[2,3]

TdDM(AS)

/DM Valid to /AS Fall Delay

[2,3]

Notes:

[1] When using extended memory timing add 2 TpC.
[2] Timing numbers given are for minimum TpC.
[3] See clock cycle dependent characteristics table.
Standard Test Load
All timing references use 2.0 V for a logic 1 and 0.8 V for a logic 0.

Clock Dependent Formulas

Number

Symbol

Equation

TdA(AS)

0.40 TpC + 0.32

TdAS(A)

0.59 TpC 3.25

TdAS(DR)

2.83 TpC + 6.14

TwAS

0.66 TpC 1.65

TwDSR

2.33 TpC 10.56

TwDSW

1.27 TpC + 1.67

TdDSR(DR)

1.97 TpC 42.5

TdDS(A)

0.8 TpC

TdDS(AS)

0.59 TpC 3.14

TdR/W(AS)

0.4 TpC

TdDS(R/W)

0.8 TpC 15

TdDW(DSW)

0.4 sTpC

TdDS(DW)

0.88 TpC 19

TdA(DR)

4 TpC 20

TdAS(DS)

0.91 TpC 10.7

TdDM(AS)

0.9 TpC 26.3

Z86E61/E63 Z8

MCU

WITH

16K/32K EPROM

P R E L I M I N A R Y

Clock

TIN

IRQN

AC CHARACTERISTICS

Additional Timing Diagram

AC CHARACTERISTICS

Additional Timing Table

= 0

C to +70

16 MHz

20 MHz

Symbol

Parameter

Min

Max

Min

Max

Units

Notes

TpC

Input Clock Period

62.5

1000

[1]

TrC,TfC

Clock Input Rise & Fall Times

[1]

TwC

Input Clock Width

[1]

TwTinL

Timer Input Low Width

[2]

TwTinH

Timer Input High Width

5TpC

[2]

TpTin

Timer Input Period

8TpC

[2]

TrTin,TfTin

Timer Input Rise & Fall Times

100

[2]

TwIL

Interrupt Request Input Low Times

[2,4]

TwIL

Interrupt Request Input Low Times

5TpC

[2,5]

TwIH

Interrupt Request Input High Times

5TpC

[2,3]

Notes:

[1] Clock timing references use 3.8V for a logic 1 and 0.8V for a logic 0.
[2] Timing references use 2.0V for a logic 1 and 0.8V for a logic 0.
[3] Interrupt references request through Port 3.
[4] Interrupt request through Port 3 (P33-P31).
[5] Interrupt request through Port 30.

Figure 25. Additional Timing

Z86E61/E63 Z8

MCU

WITH

16K/32K EPROM

P R E L I M I N A R Y

Serial Data (D0 = LSB)

R240 SIO

Count Mode
0 T1 Single Pass
1 T1 Modulo N

Clock Source
1 T1 Internal
0 T1 External Timing Input
(T

) Mode

Prescaler Modulo
(Range: 1-64 Decimal
01-00 HEX)

R243 PRE1

T0 Initial Value
(When Written)
(Range: 1-256 Decimal
01-00 HEX)
T0 Current Value
(When Read)

R244 T0

0 T0 Single Pass
1 T0 Modulo N

Count Mode

Reserved (Must be 0)

Prescaler Modulo
(Range: 1-64 Decimal
01-00 HEX)

R245 PRE0

Z8 CONTROL REGISTER DIAGRAMS

Figure 33. Prescaler 0 Register

(F5

: Write Only)

Figure 28. Serial I/O Register

(F0

: Read/Write)

0 Disable T0 Count
1 Enable T0 Count

0 No Function
1 Load T0

0 No Function
1 Load T1

0 Disable T1 Count
1 Enable T1 Count

Modes

00 External Clock Input
01 Gate Input
10 Trigger Input
(Non-retriggerable)
11 Trigger Input
(Retriggerable)

OUT

Modes

00 Not Used
01 T0 Out
10 T1 Out
11 Internal Clock Out

R241 TMR

Figure 29. Timer Mode Register

(F1

: Read/Write)

T1 Initial Value
(When Written)
(Range: 1-256 Decimal
01-00 HEX)
T1 Current Value
(When Read)

R242 T1

Figure 30. Counter/Timer 1 Register

(F2

: Read/Write)

Figure 31. Prescaler 1 Register

(F3

: Write Only)

Figure 32. Counter/Timer 0 Register

(F4

: Read/Write)

Z86E61/E63 Z8

MCU

WITH

16K/32K EPROM

P R E L I M I N A R Y

Z8 CONTROL REGISTER DIAGRAMS

(Continued)

- P2

I/O Definition

0 Defines Bit as Output
1 Defines Bit as Input

R246 P2M

Figure 34. Port 2 Mode Register

(F6

: Write Only)

Figure 36. Port 0 and 1 Mode Register

(F8

: Write Only)

R247 P3M

0 Port 2 Pull-Ups Open Drain
1 Port 2 Pull-Ups Active

0 Parity Off
1 Parity On

0 P32 = Input
P35 = Output
1 P32 = /DAV0/RDY0
P35 = RDY0//DAV0

0 P31 = Input (TIN)
P36 = Output (TOUT)
1 P31 = /DAV2/RDY2
P36 = RDY2//DAV2

0 P30 = Input
P37 = Output
1 P30 = Serial In
P37 = Serial Out

Reserved (Must be 0)

00 P33 = Input
P34 = Output
01 P33 = Input
10 P34 = /DM
11 P33 = /DAV1/RDY1
P34 = RDY1//DAV1

Figure 35. Port 3 Mode Register

(F7

: Write Only)

Interrupt Group Priority

Reserved = 000
C > A > B = 001
A > B > C = 010
A > C > B = 011
B > C > A = 100
C > B > A = 101
B > A > C = 110
Reserved = 111

IRQ3, IRQ5 Priority (Group A)

0 IRQ5 > IRQ3
1 IRQ3 > IRQ5

IRQ0, IRQ2 Priority (Group B)

0 IRQ2 > IRQ0
1 IRQ0 > IRQ2

IRQ1, IRQ4 Priority (Group C)

0 IRQ1 > IRQ4
1 IRQ4 > IRQ1

Reserved (Must be 0)

R249 IPR

Figure 37. Interrupt Priority Register

(F9

: Write Only)

R248 P01M

- P0

Mode

00 Output
01 Input
1X A

- A

Stack Selection
0 External
1 Internal

- P1

Mode

00 Byte Output
01 Byte Input
10 AD

- AD

11 High-Impedance AD

- DA

/AS, /DS, /R//W, A

- A

, If Selected

- P0

Mode

00 Output
01 Input
1X A

- A

Reserved (Must be 0)

Z86E61/E63 Z8

MCU

WITH

16K/32K EPROM

P R E L I M I N A R Y

R253 RP

0 Reserved (Must be 0)

R250 IRQ

Reserved (Must be 0)

IRQ0 = P32 Input (D0 = IRQ0)
IRQ1 = P33 Input
IRQ2 = P31 Input
IRQ3 = P30 Input, Serial Input
IRQ4 = T0 Serial Output
IRQ5 = T1

Figure 38. Interrupt Request Register

(FA

: Read/Write)

1 Enables RAM Protect

1 Enables IRQ5-IRQ0
(D

= IRQ0)

1 Enables Interrupts

R251 IMR

Figure 39. Interrupt Mask Register

(FB

: Read/Write)

R252 FLAGS

User Flag F1

User Flag F2

Half Carry Flag

Decimal Adjust Flag

Overflow Flag

Sign Flag

Zero Flag

Carry Flag

Figure 40. Flag Register

(FC

: Read/Write)

Figure 41. Register Pointer Register

(FD

: Read/Write)

Stack Pointer Upper
Byte (SP

- SP

)

R254 SPH

Figure 42. Stack Pointer Register

(FE

: Read/Write)

Stack Pointer Lower
Byte (SP

- SP

)

R255 SPL

Figure 43. Stack Pointer Register

(FF

: Read/Write)

Z86E61/E63 Z8

MCU

WITH

16K/32K EPROM

P R E L I M I N A R Y

INSTRUCTION SET NOTATION

Addressing Modes.

The following notation is used to

describe the addressing modes and instruction opera-
tions as shown in the instruction summary.

Symbol

Meaning

IRR

Indirect register pair or indirect working
register pair address

Irr

Indirect working register pair only

Indexed address

Direct address

Relative address

Immediate

Working register address only

Indirect register or indirect
working register address

Indirect working register address only

Symbols.

The following symbols are used in describing

the instruction set.

Symbol

Meaning

dst

Destination location or contents

src

Source location or contents

Condition Code

Indirect address prefix

Stack Pointer

Program Counter

FLAGS

Flag Register (Control Register 252)

IMR

Interrupt Mask Register (R251)

Flags.

Control register (R252) contains the following six

flags:

Symbol

Meaning

Carry flag

Zero flag

Sign flag

Overflow flag

Decimal-adjust flag

Half-carry flag

Affected flags are indicated by:

Clear to zero

Set to one

Set to clear according to operation

Unaffected

Undefined

Z86E61/E63 Z8

MCU

WITH

16K/32K EPROM

P R E L I M I N A R Y

MODE

dst/src

OPC

dst

OPC

MODE

OPC

src

dst

OPC

VALUE

OPC

MODE

src/dst

dst/src

OPC

src/dst

dst/src

OPC

VALUE

dst

OPC

dst/CC

7FH

FFH

6FH

OPC

dst

dst/src

1 1 1 0

dst

1 1 1 0

src

1 1 1 0

MODE

src

OPC

dst

MODE

dst

OPC

VALUE

OPC

src

MODE

dst

OPC

MODE

ADDRESS

dst/src

OPC

DAU

DAL

DAU

DAL

OPC

src

1 1 1 0

dst

1 1 1 0

dst

1 1 1 0

src

1 1 1 0

dst

1 1 1 0

CLR, CPL, DA, DEC,
DECW, INC, INCW,
POP, PUSH, RL, RLC,
RR, RRC, SRA, SWAP

JP, CALL (Indirect)

SRP

ADC, ADD, AND, CP,
OR, SBC, SUB, TCM,
TM, XOR

LD, LDE, LDEI,
LDC, LDCI

DJNZ, JR

STOP/HALT

CALL

ADC, ADD, AND, CP,
LD, OR, SBC, SUB,
TCM, TM, XOR

One-Byte Instructions

Two-Byte Instructions

Three-Byte Instructions

CCF, DI, EI, IRET, NOP,
RCF, RET, SCF

INSTRUCTION FORMATS

INSTRUCTION SUMMARY

Note:

Assignment of a value is indicated by the symbol

". For example:

dst

dst + src

indicates that the source data is added to the destination
data and the result is stored in the destination location. The

notation "addr (n)" is used to refer to bit (n) of a given
operand location. For example:

dst (7)

refers to bit 7 of the destination operand.

Z86E61/E63 Z8

MCU

WITH

16K/32K EPROM

P R E L I M I N A R Y

INSTRUCTION SUMMARY

Address

Opcode

Instruction

Mode

Byte

Flags Affected

and Operation

dst src

(Hex)

C Z S V D H

ADC dst, src

1[ ]

T T T T

dst

dst + src +C

ADD dst, src

0[ ]

T T T T

dst

dst + src

AND dst, src

5[ ]

T T

0 - -

dst

dst AND src

CALL dst

- -

SP 2

IRR

@SP

PC,

dst

CCF

- -

NOT C

CLR dst

- -

dst

COM dst

T T

0 - -

dst

NOT dst

CP dst, src

A[ ]

T T T T

- -

dst src

DA dst

T T T

X - -

dst

DA dst

DEC dst

T T T

- -

dst

dst 1

DECW dst

T T T

- -

dst

dst 1

- -

IMR(7)

DJNZr, dst

- -

r 1

r = 0 - F

if r

PC + dst

Range: +127,
128

- -

IMR(7)

HALT

- -

Address

Opcode

Instruction

Mode

Byte

Flags Affected

and Operation

dst src

(Hex)

C Z S V D H

INC dst

T T T

- -

dst

dst + 1

r = 0 F

INCW dst

T T T

- -

dst

dst + 1

IRET

T T T T T T

FLAGS

@SP;

SP + 1

@SP;

SP + 2;

IMR(7)

JP cc, dst

- -

if cc is true,

c = 0 F

dst

IRR

JR cc, dst

- -

if cc is true,

c = 0 F

PC + dst

Range: +127,
128

LD dst, src

- -

dst

src

r9
r = 0 F

LDC dst, src

Irr

- -

dst

src

LDCI dst, src

Irr

- -

dst

src

r + 1;

rr + 1

Z86E61/E63 Z8

MCU

WITH

16K/32K EPROM

P R E L I M I N A R Y

INSTRUCTION SUMMARY

(Continued)

Address

Opcode

Instruction

Mode

Byte

Flags Affected

and Operation

dst src

(Hex)

C Z S V D H

NOP

- -

OR dst, src

4[ ]

T T 0

- -

dst

dst OR src

POP dst

- -

dst

@SP;

SP + 1

PUSH src

- -

SP 1;

@SP

src

RCF

0 -

- -

RET

- -

@SP;

SP + 2

RL dst

T T T T

- -

RLC dst

T T T T

- -

RR dst

T T T T

- -

RRC dst

T T T T

- -

SBC dst, src

3[ ]

T T T T

dst

src

SCF

1 -

- -

SRA dst

T T T

0 - -

SRP dst

- -

src

Address

Opcode

Instruction

Mode

Byte

Flags Affected

and Operation

dst src

(Hex)

C Z S V D H

STOP

1 -

- -

SUB dst, src

2[ ]

[

1 [

dst

src

SWAP dst

T T

X - -

TCM dst, src

6[ ]

T T

0 - -

(NOT dst)
AND src

TM dst, src

7[ ]

T T

0 - -

dst AND src

XOR dst, src

B[ ]

T T

0 - -

dst

XOR src

These instructions have an identical set of addressing modes, which
are encoded for brevity. The first opcode nibble is found in the instruction
set table above. The second nibble is expressed symbolically by a `[ ]'
in this table, and its value is found in the following table to the left of the
applicable addressing mode pair.

For example, the opcode of an ADC instruction using the addressing
modes r (destination) and Ir (source) is 13.

Address Mode

Lower

dst

src

Opcode Nibble

[2]

[3]

[4]

[5]

[6]

[7]

Z86E61/E63 Z8

MCU

WITH

16K/32K EPROM

P R E L I M I N A R Y

6.5

DEC

6.5

DEC

IR1

6.5

ADD

r1, r2

6.5

ADD

r1, Ir2

10.5

ADD

R2, R1

10.5

ADD

IR2, R1

10.5

ADD

R1, IM

10.5

ADD

IR1, IM

Lower Nibble (Hex)

Upper Nibble (Hex)

Bytes per Instruction

6.5

RLC

6.5

RLC

IR1

6.5

ADC

r1, r2

6.5

ADC

r1, Ir2

10.5

ADC

R2, R1

10.5

ADC

IR2, R1

10.5

ADC

R1, IM

10.5

ADC

IR1, IM

6.5

INC

6.5

INC

IR1

6.5

SUB

r1, r2

6.5

SUB

r1, Ir2

10.5

SUB

R2, R1

10.5

SUB

IR2, R1

10.5

SUB

R1, IM

10.5

SUB

IR1, IM

10.5

DECW

RR1

10.5

DECW

IR1

6.5

IR1

10.5

INCW

RR1

10.5

INCW

IR1

6.5

r1, r2

6.5

r1, Ir2

10.5

R2, R1

10.5

IR2, R1

10.5

R1, IM

10.5

IR1, IM

6.5

CLR

6.5

CLR

IR1

6.5

XOR

r1, r2

6.5

XOR

r1, Ir2

10.5

XOR

R2, R1

10.5

XOR

IR2, R1

10.5

XOR

R1, IM

10.5

XOR

IR1, IM

6.5

RRC

6.5

RRC

IR1

12.0

LDC

r1, Irr2

18.0

LDCI

Ir1, Irr2

10.5

r1,x,R2

6.5

SRA

6.5

SRA

IR1

20.0

CALL*

IRR1

20.0

CALL

10.5

r2,x,R1

6.5

IR1

6.5

r1, IR2

10.5

R2, R1

10.5

IR2, R1

10.5

R1, IM

10.5

IR1, IM

8.5

SWAP

8.5

SWAP

IR1

6.5

Ir1, r2

10.5

R2, IR1

6.5

r1, R2

6.5

r2, R1

12/10.5

DJNZ

r1, RA

12/10.0

cc, RA

6.5

r1, IM

12.10.0

cc, DA

6.5

INC

6.0

STOP

7.0

HALT

6.1

14.0

RET

16.0

IRET

6.5

RCF

6.5

SCF

6.5

CCF

6.0

NOP

10.5

R1, R2

Lower

Opcode

Nibble

Pipeline
Cycles

Mnemonic

Second
Operand

Execution

Cycles

Upper

Opcode

Nibble

First

Operand

Legend:

R = 8-bit Address

r = 4-bit Address

R1 or r1 = Dst Address

R2 or r2 = Src Address

Sequence:

Opcode, First Operand,

Second Operand

Note:

Blank areas not defined.

2-byte instruction appears as

a 3-byte instruction

8.0

IRR1

6.1

SRP

6.5

SBC

r1, r2

6.5

SBC

r1, Ir2

10.5

SBC

R2, R1

10.5

SBC

IR2, R1

10.5

SBC

R1, IM

10.5

SBC

IR1, IM

8.5

IR1

6.5

r1, r2

6.5

r1, Ir2

10.5

R2, R1

10.5

IR2, R1

10.5

R1, IM

10.5

IR1, IM

10.5

POP

10.5

POP

IR1

6.5

AND

r1, r2

6.5

AND

r1, Ir2

10.5

AND

R2, R1

10.5

AND

IR2, R1

10.5

AND

R1, IM

10.5

AND

IR1, IM

6.5

COM

6.5

COM

IR1

6.5

TCM

r1, r2

6.5

TCM

r1, Ir2

10.5

TCM

R2, R1

10.5

TCM

IR2, R1

10.5

TCM

R1, IM

10.5

TCM

IR1, IM

10/12.1

PUSH

12/14.1

PUSH

IR2

6.5

r1, r2

6.5

r1, Ir2

10.5

R2, R1

10.5

IR2, R1

10.5

R1, IM

10.5

IR1, IM

12.0

LDC

r1, Irr2

18.0

LDCI

Ir1, Irr2

12.0

LDE

r1, Irr2

18.0

LDEI

Ir1, Irr2

12.0

LDE

r2, Irr1

18.0

LDEI

Ir2, Irr1

OPCODE MAP

Z86E61/E63 Z8

MCU

WITH

16K/32K EPROM

P R E L I M I N A R Y

ORDERING INFORMATION

Z86E61

16 MHz

20 MHz

40-Pin DIP

44-Pin PLCC

40-Pin DIP

44-Pin PLCC

Z86E6116PSC

Z86E6116VSC

Z86E6120PSC

Z86E6120VSC

44-Pin QFP

Z86E6116FEC

Z86E63

16 MHz

20 MHz

40-Pin DIP

44-Pin PLCC

40-Pin DIP

44-Pin PLCC

Z86E6316PSC

Z86E6316VSC

Z86E6320PSC

Z86E6320VSC

For fast results, contact your local Zilog sales office for assistance in ordering the part desired.

CODES

Preferred Package

P = Plastic DIP
V = Plastic Chip Carrier

Temperature

S = 0

C to +70

Speeds

12 = 16 MHz
16 = 20 MHz

Environmental

C = Plastic Standard

Example:

Z 86E61 16 P S C

is an Z86E61, 16 MHz, DIP, 0

C to +70

C, Plastic Standard Flow

Environmental Flow
Temperature
Package
Speed
Product Number
Zilog Prefix

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: Z86E61

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: Z86E61

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: Z86E61