CP96TEL0607
P R E L I M I N A R Y
1-1
1
P
RELIMINARY
C
USTOMER
P
ROCUREMENT
S
PECIFICATION
Z89332
1
D
IGITAL
T
ELEVISION
C
ONTROLLER
FEATURES
s
42-Pin SDIP and 48-Pin Ceramic Packages with
42- to 48-Pin Adapter Socket
s
0
C to +70
C Temperature Range
s
Fully Customized Character Set
s
Character-Control and Closed-Caption Modes
s
Keypad User Control
s
TV Tuner Serial Interface
s
Direct Video Signals
s
Speed: 12 MHz
GENERAL DESCRIPTION
The Z89332 Digital Television Controller is designed to
provide complete audio and video control of television re-
ceivers, video recorders, and advanced on-screen display
facilities. The television controller features a Z89C00 RISC
processor core that controls the on-board peripheral func-
tions and registers using the standard processor instruc-
tion set.
Character attributes can be controlled through two modes:
the on-screen display Character-Control Mode and the
Closed-Caption Mode. The Character-Control Mode pro-
vides access to the full set of attribute controls, allowing the
modification of attributes on a character-by-character ba-
sis. The insertion of control characters permits direction of
other character attributes. Closed-caption text can be de-
coded directly from the composite video signal and dis-
played on-screen with the assistance of the processor's
digital signal processing (DSP) capabilities.
The fully customized 512 character set, formatted in two
256 character banks, can be displayed with a host of dis-
play attributes that include underlining, italics, blinking,
eight foreground/background colors, character position off-
set delay, and background transparency.
Serial interfacing with the television tuner is provided
through the tuner serial port. Other serial devices, such as
digital channel tunning adjustments, may be accessed
through the industry-standard I
2
C port.
User control can be monitored through the keypad scan-
ning port, or the 16-bit remote control capture register. Re-
ceiver functions such as color and volume can be directly
controlled by eight 8-bit pulse width modulated ports.
Notes:
All Signals with a preceding front slash, "/", are active Low,
e.g.: B//W (WORD is active Low); /B/W (BYTE is active
Low, only).
Power connections follow conventional descriptions be-
low:
Device
ROM
(KW)
RAM*
(Words)
PWM
(8-Bit)
Voltage
Range
Z89332
24
640
8
4.5 to 5.5V
Note:
*General-Purpose
Connection
Circuit
Device
Power
V
CC
V
DD
Ground
GND
V
SS
Z89332
Digital Television Controller
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P R E L I M I N A R Y
CP96TEL0607
GENERAL DESCRIPTION
(Continued)
Figure 1. Functional Block Diagram
Capture
IRIN
ADC
ADC0
ADC1
ADC2
ADC3
ADC4
Port 0
Port 00
Port 01
Port 02
Port 03
Port 04
Port 05
Port 06
Port 07
Port 08
Port 09
Port 0F
Control
XTAL1
XTAL2
LPF
HSYNC
VSYNC
/Reset
CPU
RAM
640 x 16
ROM
24K x 16
OSD
V1
V2
V3
VBLANK
HALFBLNK
PWM
PWM1
PWM2
PWM3
PWM4
PWM5
PWM9
PWM10
Port1
Port 10
Port 11
Port 12
Port 13
Port 14
Port 15
Port 16
Port 17
Port 18
Port 17
Port 00
Register Addr/Data
Address
Data
ROM Data
ROM Addr
Port0F
Z89332
Digital Television Controller
CP96TEL0607
P R E L I M I N A R Y
1-3
1
PIN DESCRIPTION
Figure 2. 42-Pin Shrink DIP and 48-Pin Ceramic Pin Configurations
with 42- to 48-Pin Adapter Footprint
1
2
9
3
4
5
6
7
8
42
41
40
39
38
37
36
35
34
Port12/I2MSD
P11/I2MSC
Vcc
Port02/I2SSD
Port01/I2SSC
Port09
Port08/R<1>
IRIN
Port07/CSync
PWM10
PWM9
PWM4
PWM3
PWM2
PWM1
Port03
33
32
31
30
29
14
10
11
12
13
PWM5
Port00/ADC2
Port17/ADC1
GND
Port10/R<0>
/Reset
XTAL2
XTAL1
ANGND
LPF
15
28
27
26
25
24
23
20
16
17
18
19
Port04/ADC4
Port05/ADC3
Port06/Counter
Port18/G<0>
Port15/B<1>
Port16/SCLK
Port14/B<0>
Port13/G<1>
HSync
CVI/ADC0
VSync
VBlank
V1
V2
Z89332
Shrink
DIP
22
21
Port0F/HalfBlnk
V3
Z89332
Digital Television Controller
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P R E L I M I N A R Y
CP96TEL0607
Table 1. 42-Pin SDIP Pin Identification
Name
Function
Z89332
Direction
Reset
Notes
V
CC
+ 5 Volts
34
PWR
GND
0 Volts
13, 30
PWR
IRIN
Infrared Remote Capture
Input
36
I
I
ADC[4:0]
4-Bit A/D Converter Input
9, 10, 11, 12, 28
AI
I
PWM10, PWM9
14-Bit Pulse Width
Modulator Output
1, 2
O
O
PWM[5:1]
8-Bit Pulse Width Modulator
Output
3, 4, 5, 6, 7
OD/O*
O
Port0[F:0]
Bit Programmable
Input/Output Ports
21, -, -, -, -, -, 38, 37,
35, -, -, 15, 8, 40, 39,
11
B
I
[1]
Port1[8:0]
Bit Programmable
Input/Output Ports
16, 12, 20, 19, 18, 17,
42, 41, 14
B
I
SCL
I
2
C Clock I/O
39 or 41
BOD
[2]
SCD
I
2
C Data I/O
40 or 42
BOD
[3]
XTAL1
Crystal Oscillator Input
31
AI
I
XTAL2
Crystal Oscillator Output
32
AO
O
LPF
Loop Filter
29
AB
O
HSYNC
H_SYNC
26
B
I
VSYNC
V_SYNC
27
B
I
/Reset
Device Reset
33
I
I
V[3:1]
OSD Video Output Typically
Drive B, G, and R Outputs
22, 23, 24
O
O
Blank
OSD Blank Output
25
O
O
HalfBlank
OSD Half-Blank Outpu
21
O
[4]
RGB Digital
Outputs
R[1:0], G[1:0], and B[1:0]
Outputs of the RGB Matrix
37, 14, 17, 16, 19, 18
O
[5]
SCLK
Internal Processor SCLK
20
O
[6]
Notes:
1) Port 0 [E:A] is not available on the 42-pin SDIP version.
2) SCL I/O pin is shared with Port 0 or Port 11.
3) SCD I/O pin is shared with Port 02 or Port 12.
4) Half Blank output is a function shared with Port 0F.
5) Digital RGB outputs and the internal SCLK are shared with Port 1 [5:0].
6) Internal processor SCLK is shared with Port 16.
* PWM outputs are push/pull in Revision Z89332EA and later.
Z89332
Digital Television Controller
CP96TEL0607
P R E L I M I N A R Y
1-5
1
V1, V2, V3 ANALOG OUTPUT
Specifications V
CC
= 5.25V and V
CC
= 4.75V
V
CC
= 5.25V
Condition
Limit
Output Voltage
Bit = 11
4.2V
0.4V
Bit = 10
45% 0.15V to 55% of actual data = 11 value
Bit = 01
0.60 V
0.4V
Bit = 00
74% to 89% of actual data = 11 value
Setting Time
70% of DC Level, 10 pF Load
< 50 nsec
V
CC
= 4.75V
Condition
Limit
Output Voltage
Bit = 11
3.6V
0.4V
Bit = 10
45% 0.15V to 55% of actual data = 11 value
Bit = 01
0.60V
0.4V
Bit = 00
74% to 89% of actual data = 11 value
Setting Time
70% of DC Level, 10 pF Load
< 50 nsec
Figure 3. 32K Oscillator Recommended Circuit
Figure 4. Recommended Low Pass Filter Circuit
Z893XX
XTAL1
XTAL2
68 K
47 pF
10 pF
10 M
32.768kHz
Z893XX
47
F
510
0.1
F
Z89332
Digital Television Controller
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P R E L I M I N A R Y
CP96TEL0607
ABSOLUTE MAXIMUM RATINGS
DC CHARACTERISTICS
T
A
= 0
C to + 70
C; V
CC
= 4.5V to + 5.5V; F
OSC
= 32.768 KHz
Symbol
Parameter
Min
Max
Units
Conditions
V
CC
Power Supply Voltage
0
7
V
V
ID
Input Voltage
0.3
V
CC
+0.3
V
Digital Inputs
V
IA
Input Voltage
0.3
V
CC
+0.3
V
Analog Inputs (A/D0...A/D4)
V
O
Output Voltage
0.3
V
CC
+0.3
V
All Push-Pull Digital Output
V
O
Output Voltage
0.3
V
CC
+8
Open-Drain PWM Outputs
(PWM1...PWM8)
V
O
Output Voltage
0.3
V
CC
+0.3
V
Push/Pull PWM Outputs
(PWM1...PWM8) = Z89332EA
and Later Revisions
I
OH
Output Current High
10
mA
One Pin
I
OH
Output Current High
100
mA
All Pins
I
OL
Output Current Low
20
mA
One Pin
I
OL
Output Current Low
200
mA
All Pins
T
A
Operating Temperature
0
70
C
T
A
Storage Temperature
65
150
C
Symbol
Parameter
Min
Max
Typical
Units
Conditions
V
IL
Input Voltage Low
0
0.2 V
CC
0.4
V
V
IH
Input Voltage High
0.7 V
CC
V
CC
3.6
V
V
PU
Max. Pull-Up Voltage
V
CC
+0.3
V
All Pins
V
OL
Output Voltage Low
0.4
0.16
V
@ I
OL
= 1 mA
V
OH
Output Voltage High
V
CC
0.4
4.75
V
@ I
OL
= 0.75 mA
V
XL
Input Voltage XTAL1 Low
0.3 V
CC
1.0
V
External Clock
V
XH
Input Voltage XTAL1 High
V
CC
2.0
3.5
V
Generator Driven
V
HY
Schmitt Hysteresis
3.0
0.75
0.5
V
On XTAL1 Input Pin
I
IR
Reset Input Current
150
90
A
V
RL
= 0V
I
IL
Input Leakage
3.0
3.0
0.01
A
@ 0V and V
CC
I
CC
Supply Current
100
60
mA
I
ADC
Input Current
0.5
mA
AE Revision
I
ADC
Input Current
10
A
CC,CA,EA & Later Rev.
Notes:
A) The Z89332 should not be operated for extended periods with the crystal oscillator disconnected, except in the defined
power-down modes. In the event that the Z89332 is operated with the oscillator disconnected, the device may draw higher
than typical current.
B) Each line of the on-screen display can consist of any number of characters, up to a maximum of 30 characters.
Z89332
Digital Television Controller
CP96TEL0607
P R E L I M I N A R Y
1-7
1
AC CHARACTERISTICS
T
A
= 0
C to + 70
C; V
CC
= 4.5V to 5.5V; F
OSC
= 32.768 KHz
AC CHARACTERISTICS
T
A
= 0
C to + 70
C; V
CC
= 4.5V to 5.5V; F
OSC
= 32.768 KHz
Symbol
Parameter
Min
Max
Typical
Units
T
P
C
Input Clock Period
16
100
32
S
T
R
C,T
F
C
Clock Input Rise and Fall
12
S
T
D
POR
Power-On Reset Delay
0.8
1.2
Sec
Symbol
Parameter
Min
Max
Typical
Units
T
W
RES
Power-On Reset Min. Width
5 TPC
S
T
D
H
S
H_Sync Incoming Signal Width
5.5
12.5
11
S
T
D
V
S
V_Sync Incoming Signal Width
0.15
1.5
1.0
mS
T
D
E
S
Time Delay Between Leading Edge of V_Sync and H_Sync in Even Field
12
+12
0
S
T
D
O
S
Time Delay Between Leading Edge of H_Sync in Odd Field
20
44
32
S
T
W
HV
S
H_Sync/V_Sync Edge Width
2.0
0.5
S
Note:
All timing of the I
2
C bus interface are defined by related specifications of the I
2
C bus interface.
Z89332
Digital Television Controller
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P R E L I M I N A R Y
CP96TEL0607
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