U6216A
1
December 12, 1997
Standard 2K x 8 SRAM
Features
F
2048 x 8 bit static CMOS RAM
F
70 and 85 ns Access Times
F
Common data inputs and data
outputs
F
Three-state outputs
F
Typ. operating supply current
70 ns: 30 mA
85 ns: 28 mA
F
Data retention current at 3 V:
< 10
A (standard)
F
Standby current standard < 30
A
F
Standby current low power (L)
< 5
A
F
Standby current for L-version at
25
C and 5 V: typ. 50 nA
F
TTL/CMOS-compatible
F
Automatical reduction of power-
dissipation in long Read or Write
cycles
F
Power supply voltage 5 V
F
Operating temperature ranges
0 to 70
C
-40 to 85
C
F
CECC 90000 Quality Standard
F
ESD protection > 2000 V
(MIL STD 883C M3015.7)
F
Latch-up immunity >100 mA
F
Packages: PDIP24 (600 mil)
SOP24 (300 mil)
Description
The U6216A is a static RAM manu-
factured using a CMOS process
technology with the following ope-
rating modes:
- Read - Standby
- Write - Data Retention
The memory array is based on a
6-transistor cell.
The circuit is activated by the fal-
ling edge of E. The address and
control inputs open simultaneously.
According to the information of W
and G, the data inputs, or outputs,
are active. During the active state
E = L each address change leads
to a new Read or Write cycle. In a
Read cycle, the data outputs are
activated by the falling edge of G,
afterwards the data word read will
be available at the outputs
DQ0 - DQ7. After the address
change, the data outputs go High-Z
until the new information read is
available. The data outputs have
no preferred state. If the memory is
driven by CMOS levels in the
active state, and if there is no
change of the address, data input
and control signals W or G, the
operating current (I
O
= 0 mA) drops
to the value of the operating cur-
rent in the Standby mode. The
Read cycle is finished by the falling
edge of W, or by the rising edge of
E, respectively.
Data retention is guaranteed down
to 2 V. With the exception of E, all
inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required.
1
A7
VCC
24
2
A6
A8
23
4
A4
W
21
5
A3
G (OE)
20
3
A5
A9
22
6
A2
A10
19
7
A1
18
8
A0
DQ7
17
9
DQ0
DQ6
16
10
DQ1
DQ5
15
11
DQ2
DQ4
14
12
VSS
DQ3
13
Pin Configuration Pin Description
Signal Name Signal Description
A0 - A10 Address Inputs
DQ0 - DQ7 Data In/Out
E
Chip Enable
G
Output Enable
W
Write Enable
VCC Power Supply Voltage
VSS Ground
E
(CE)
Top View
PDIP
SOP
U6216A
2
December 12, 1997
* H or L
Operating Mode E
W
G
DQ0 - DQ7
Standby/not selected
H
*
*
High-Z
Internal Read L H H High-Z
Read L H L Data Outputs
Low-Z
Write L L
*
Data Inputs High-Z
Truth Table
Block Diagram
A4
A5
A6
A7
A8
A9
A10
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
V
CC
Memory Cell
Array
128 Rows x
128 Columns
Maximum Ratings Symbol Min. Max.
Unit
Power Supply Voltage V
CC
-0.5 7 V
Input Voltage V
I
-0.5 V
CC
+ 0.5 V
Output Voltage V
O
-0.5 V
CC
+ 0.5 V
Power Dissipation P
D
1
W
Operating
Temperature
C-Type
K-Type
T
a
0
-40
70
85
C
C
Storage Temperature T
stg
-55 125
C
A0
A1
A2
A3
V
SS
W
G
Characteristics
E
Ro
w A
d
d
r
e
s
s
I
npu
t
s
C
o
l
u
m
n
Addr
es
s
I
n
put
s
Address
Change
Detector
C
o
lu
mn
De
c
o
d
e
r
R
o
w De
c
o
d
e
r
Sense Amplifier/
Write Control Logic
Clock
Generator
C
o
m
m
o
n
D
a
ta
I/
O
All voltages are referenced to V
SS
= 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of
5 ns, measured between 10 % and 90 % of V
I
, as well as
input levels of V
IL
= 0 V and V
IH
= 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the t
dis
-times and t
t(QX )
, in which cases transition is measured
200 mV from steady-state voltage.
U6216A
3
December 12, 1997
* -1 V at Pulse Width 50 ns
Recommended
Operating Conditions
Symbol Conditions Min. Max. Unit
Power Supply Voltage V
CC
4.5 5.5 V
Data Retention Voltage V
CC(DR)
2.0 V
Input Low Voltage* V
IL
-0.3 0.8 V
Input High Voltage V
IH
2.2 V
CC
+ 0.3 V
Electrical Characteristics Symbol Conditions Min. Max. Unit
Supply Current - Operating Mode
Supply Current - Standby Mode
(CMOS level)
Standard
Low Power (L)
Supply Current - Standby Mode
(TTL level)
Supply Current - Data Retention
Mode (Standard)
I
CC(OP)
I
CC(SB)
I
CC(SB)1
I
CC(DR)
V
CC
V
IL
V
IH
t
cW
V
CC
V
(E)
V
CC
V
(E)
V
CC(DR)
V
(E)
= 5.5 V
= 0.8 V
= 2.2 V
= 70 ns
= 85 ns
= 5.5 V
= V
CC
- 0.2 V
= 5.5 V
= 2.2 V
= 3 V
= 2 V
= V
CC(DR)
- 0.2 V
50
45
30
5
3
10
5
mA
mA
A
A
mA
A
A
Output High Voltage
Output Low Voltage
V
OH
V
OL
V
CC
I
OH
V
CC
I
OL
= 4.5 V
= -1.0 mA
= 4.5 V
= 4.0 mA
2.4
0.4
V
V
Input High Leakage Current
Input Low Leakage Current
I
IH
I
IL
V
CC
V
IH
V
CC
V
IL
= 5.5 V
= 5.5 V
= 5.5 V
=
0 V
-2
2
A
A
Output High Current
Output Low Current
I
OH
I
OL
V
CC
V
OH
V
CC
V
OL
= 4.5 V
= 2.4 V
= 4.5 V
= 0.4 V
4
-1 mA
mA
Output Leakage Current
High at Three-State Outputs
Low at Three-State Outputs
I
OHZ
I
OLZ
V
CC
V
OH
V
CC
V
OL
= 5.5 V
= 5.5 V
= 5.5 V
=
0 V
-2
2
A
A
U6216A
4
December 12, 1997
Switching Characteristics
Symbol Min. Max.
Unit
Alt.
IEC
07
08
07
08
Time to Output in Low-Z t
LZ
t
t(QX)
5 5 10 10 ns
Cycle Time
Write Cycle Time
Read Cycle Time
t
WC
t
RC
t
cW
t
cR
70
70
85
85
ns
ns
Access Time
E LOW to Data Valid
G LO W to Data Valid
Address to Data Valid
t
ACE
t
OE
t
AA
t
a(E)
t
a(G)
t
a(A)
70
35
70
85
45
85
ns
ns
ns
Pulse Widths
Write Pulse Width
Chip Enable to End of Write
t
WP
t
CW
t
w(W)
t
w(E)
40
45
50
55
ns
ns
Setup Times
Address Setup Time
Chip Enable to End of Write
Write Pulse Width
Data Setup Time
t
AS
t
CW
t
WP
t
DS
t
su(A)
t
su(E)
t
su(W)
t
su(D)
0
45
40
30
0
55
50
30
ns
ns
ns
ns
Data Hold Time
Address Hold from End of Write
t
DH
t
AH
t
h(D)
t
h(A)
0
0
0
0
ns
ns
Output Hold Time from Address
Change
t
OH
t
v(A)
5
5
ns
E HIGH to Output in High-Z
W LOW to Output in High-Z
G HIGH to Output in High-Z
t
HZCE
t
HZWE
t
HZOE
t
dis(E)
t
dis(W)
t
dis(G)
0
0
0
0
0
0
30
25
30
30
30
30
ns
ns
ns
Data Retention
4.5 V
t
DR
t
rec
V
CC
E
V
CC(DR)
2 V
V
CC(DR)
- 0.2 V
V
E(DR)
V
CC(DR)
+ 0.3 V
0 V
2.2 V
2.2 V
Data Retention Mode
Chip Deselect to Data Retention Time t
DR
: min 0 ns
Operating Recovery Time t
rec:
min t
cR
U6216A
5
December 12, 1997
Example
Test Configuration for Functional Check
V
IH
V
IL
V
SS
V
CC
5 V
1.0 k
660
100 pF
1)
V
O
IC Code Numbers
U6216A L
D
K
07
1)
In measurement of t
dis(E)
, t
dis(W)
, t
dis(G)
, t
t(QX)
the capacitance is 5 pF.
The date of manufacture is given by the 4 last digits of the mark, the first 2 digits indicating the year, and the last
2 digits the calendar week.
S
i
m
u
l
t
a
neous
m
e
as
u
r
e-
m
e
n
t
of
al
l
8
out
put
p
i
ns
I
nput
l
e
v
e
l
ac
c
o
r
d
i
n
g t
o
t
h
e
r
e
l
e
v
a
nt
t
e
s
t
m
e
as
u
r
em
ent
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
E
W
G
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Capacitance Conditions Symbol Min. Max. Unit
Input Capacitance
V
CC
= 5.0 V
V
I
= V
SS
C
I
7
pF
Output Capacitance
f = 1
MHz
T
a
= 25
C
C
O
7
pF
All pins not under test must be connected with ground by capacitors.
Typ
Package
D = PDIP
S = SOP
Operating Temperature Range
C = 0 to 70 C
K = -40 to 85 C
Access Time
07 = 70 ns
08 = 85 ns
Power Consumption
= Standard
L = Low Power
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