Zentrum Mikroelektronik Dresden GmbH
Grenzstrae 28
D-01109 Dresden
P. O. B. 80 01 34
D-01101 Dresden
Germany
Phone: +49 351 8822 306
Fax: +49 351 8822 337
Email: sales@zmd-gmbh.de
http://www.zmd-gmbh.de
July 3, 1997
U635HM1024
Advanced Information
PowerStore
128K x 8 nvSRAM
Features
F
High-performance CMOS non-
volatile static RAM Module 4 x
32768 x 8 bits
F
25, 35 and 45 ns Access Times
F
10,15 and 20 ns Output Enable
Times
F
I
CC
= 50 mA at 200 ns Cycle Time
F
Automatic STORE to EEPROM
on Power Down
F
Software initiated STORE
F
Automatic STORE Timing
F
10
5
STORE cycles to EEPROM
F
10 year data retention in EEPROM
F
Automatic RECALL on Power Up
F
Software RECALL Initiation
F
Unlimited RECALL cycles from
EEPROM
F
Single 5 V
10 % Operation
F
Operating temperature range
0 to 70
C
-40 to 85
C
F
CECC 90000 Quality Standard
F
ESD characterization according
F
MIL STD 883C M3015.7-HBM
F
Packages SOP44(600 mil) Module
PDIP32(600 mil) Module
Description
The U635HM1024 has two sepa-
rate modes of operation: SRAM
mode and nonvolatile mode. In
SRAM mode, the memory operates
as an ordinary static RAM. In non-
volatile operation, data is transfer-
red in parallel from SRAM to
EEPROM or from EEPROM to
SRAM. In this mode SRAM
functions are disabled.
The U635HM1024 is a fast static
RAM (25, 35, 45 ns), with a nonvo-
latile electrically erasable PROM
(EEPROM) element incorporated
in each static memory cell.
The SRAM can be read and written
an unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation) take place
automatically upon power down
using charge stored in system
capacitance. Transfers from the
EEPROM to the SRAM (the
RECALL operation) take place
automatically on power up. The
U635HM1024 combines the high
performance and ease of use of a
fast SRAM with nonvolatile data
integrity.
STORE cycles also may be initiated
under user control via a software
sequence.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or write
accesses intervene in the sequence
or the sequence will be aborted.
RECALL cycles may also be initia-
ted by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvolatile
information is transferred into the
SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
Signal Name Signal Description
A0 - A16 Address Inputs
DQ0 - DQ7 Data In/Out
E
Chip Enable
G
Output Enable
W
Write Enable
VCC Power Supply Voltage
VSS Ground
Pin Configuration
In
p
u
t B
u
ffe
r
s
EEPROM Array
512 x (64 x 8)
STORE
RECALL
SRAM
Array
512 Rows x
64 x 8 Columns
G
E1
W
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Column I/O
Column Decoder
A0 - A13
Store/
Recall
Con trol
R
o
w De
c
o
d
e
r
A5
A6
A7
A8
A9
A11
A12
A13
A14
V
CC
V
SS
Software
Detect
Power
Con trol
V
CC
HSB
U635H256
A0 A1 A2 A3 A4
A10
Logic Block Diagram
A15
A16
E
E1
E2
E3
E4
Address
Decoder
Top View
1
44
2
43
4
41
5
40
3
42
6
39
7
38
8
37
12
33
9
36
10
35
11
34
13
32
14
31
SOP
15
30
16
29
17
28
18
27
19
26
20
25
21
22
24
23
A4
A3
A2
A1
A0
E
DQ0
DQ1
DQ2
DQ3
VCC
VSS
DQ4
DQ5
DQ6
DQ7
W
A15
A14
A13
A12
n.c.
A5
A6
A7
G
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
VSS
VCC
n.c.
n.c.
n.c.
n.c.
n.c.
A8
A9
A10
A11
n.c.
Top View
PDIP
VCC
A15
n.c.
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
n.c.
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PDF 
ZIP