56F8145 - Efficient 16-bit 56800E family controller engine with dual Harvard architecture• Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency• Single-cycle 16 Ч 16-bit parallel Multiplier-Accumulator (MAC)• Four 36-bit accumulators, including extension bits• Arithmetic and logic multi-bit shifter• Parallel instruction set with unique DSP addressing modes• Hardware DO and REP loops• Three internal address buses• Four internal data buses• Instruction set supports both DSP and controller functions•
56F8167 - Efficient 16-bit 56800E family controller engine with dual Harvard architecture• Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency• Single-cycle 16 Ч 16-bit parallel Multiplier-Accumulator (MAC)• Four 36-bit accumulators, including extension bits• Arithmetic and logic multi-bit shifter• Parallel instruction set with unique DSP addressing modes• Hardware DO and REP loops• Three internal address buses and one external address bus• Four internal data buses and one external data bus• Instr
56F8367 - Efficient 16-bit 56800E family controller engine with dual Harvard architecture• Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency• Single-cycle 16 Ч 16-bit parallel Multiplier-Accumulator (MAC)• Four 36-bit accumulators, including extension bits• Arithmetic and logic multi-bit shifter• Parallel instruction set with unique DSP addressing modes• Hardware DO and REP loops• Three internal address buses and one external address bus• Four internal data buses and one external data bus• Instr
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