DESCRIPTION:
The LP-StackTM series is a family of interchangeable memory modules. The 512 Megabit SDRAM is a member of this family which
utilizes the new and innovative space saving TSOP stacking technology. The modules are constructed with 64 Meg x 4 SDRAMs.
This 256 Megabit based LP-StackTM module, the
DPSD64MX8WY5 has been designed to fit in the same
footprint as the 32 Meg x 8 SDRAM TSOP monolithic and 64
and 128 Megabit SDRAM based family of LP-StackTM modules.
This allows the memory board designer to upgrade the
memory in their products without redesigning the memory
board, thus saving time and money.
FEATURES:
Configuration Available:
64 Meg x 8 (16M x 4 x 8 bits)
Clock Frequency:
66, 83, 100, 125, 133 MHz (max.)
PC100 and PC133 Compatible
3.3 Volt Power Supply
LVTTL Compatible I/O
Four Bank Operation
Programmable Burst Type, Burst Length, and CAS Latency
8192 Cycles / 64 ms
Auto and Self Refresh
Package: TSOP Leadless Stack
A0-A12
Row Address:
A0-A12
Column Address: A0-A9, A11
BA0,BA1
Bank Select Address
DQ0-DQ7
Data In/Data Out
CAS
Column Address Strobe
RAS
Row Address Enable
WE
Data Write Enable
DQM
Data Input/Output Mask
CKE
Clock Enable
CLK
System Clock
CS
Chip Select
Vcc/Vss
Power Supply/Ground
Vcc
Q
/Vss
Q
Data Output Power/Ground
N.C.
No Connect
30A213-10
REV. B 8/01
This document contains information on a product that is currently released to production at DPAC Technologies.
DPAC reserves the right to change products or specifications herein without prior notice.
512 Megabit Synchronous DRAM
DPSD64MX8WY5
1
33 A8
VCC
1
2
54 VSS
VCCQ
3
53
N.C.
4
52 VSSQ
DQ1
5
51 N.C.
VSSQ
6
50 DQ6
N.C.
7
49 VCCQ
8
48 N.C.
VCCQ
9
47
N.C. 10
46 VSSQ
DQ3 11
45 N.C.
VSSQ 12
44 DQ4
N.C. 13
43 VCCQ
VCC 14
42 N.C.
N.C. 15
41 VSS
WE 16
40 N.C.
CAS 17
39 DQM
RAS 18
38 CLK
CS 19
37 CKE
BA0 20
36 A12
BA1 21
35 A11
A10 22
34 A9
A0 23
32 A7
A1 24
31 A6
A2 25
30 A5
A3 26
29 A4
VCC 27
28 VSS
DQ2
DQ0
DQ5
DQ7
(TOP VIEW)
A0-A12
CAS
WE
128 Mbit
S
DRA
M
DQ1,DQ3,DQ4,DQ6
CS
(16M
x4x4bi
t)
(16M
x4x4bi
t)
RAS
CKE
CLK
DQM
DQ0,DQ2,DQ5,DQ7
BA0,BA1
1
PIN NAMES
PIN-OUT DIAGRAM
FUNCTIONAL BLOCK DIAGRAM
ADVANCED COMPONENTS PACKAGING
MANUFACTURER CODE *
P1
DP
XX
XX
-
SPEED
MEMORY
PREFIX
PC100
SD 64M
X
8
Y5
PACKAGE
MEMORY
DESIG
MEMORY
TYPE
MEMORY MODULE WITHOUT SUPPORT LOGIC
DEPTH
WIDTH
DESIG
W
STACKABLE TSOP
SYNCHRONOUS DRAM
10ns (100MHz)
8ns (125MHz)
08
10
SUPPLIER
- DP
SUPPLIER CODE *
256 MEGABIT LVTTL BASED
15
12
12ns (83MHz)
15ns (66MHz)
CL
X
GRADE
X
CAS LATENCY 2
2
Commercial Temperature
Blank
75
7.5ns (133MHz)
PART NUMBER DESCRIPTION
30A213-10
REV. B 8/01
2
TOP VIEW
SIDE VIEW
BOTTOM VIEW
END VIEW
PIN 1
INDEX
1
.502.008
.098 MAX.
.885.010
[12.75.20]
[22.48.25]
[2.45 MAX.]
DPAC Technologies Products & Services for the Integration Age
7321 Lincoln Way, Garden Grove, CA 92841 Tel 714 898 0007 Fax 714 897 1772
www.dpactech.com Nasdaq: DPAC
2001 DPAC Technologies, all rights reserved. DPAC TechnologiesTM, Memory StackTM, System StackTM, CS StackTM are trademarks of DPAC Technologies Corp.
DPSD64MX8WY5
512 Megabit Synchronous DRAM
* Contact your sales representative for supplier and manufacturer codes.
MECHANICAL DRAWING
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